Memory test system and test method thereof

Abstract

The invention provides a memory test system and a test method thereof. The memory test system includes a memory tester and a memory unit. The memory tester generates a data gating signal during testing. The memory unit detects enabling of the data gating signal during testing and outputs a test data signal having stored data to the memory tester. The memory tester judges whether the memory unit is damaged based on the test data.

Description

technical field [0001] The invention relates to a test system and a test method, in particular to a memory test system and a test method thereof. Background technique [0002] Double Data Rate (DDR) memory is a revolutionary memory technology based on Synchronous Dynamic Random Access Memory (SDRAM), which provides a high performance, low cost memory solution. Moreover, under the specifications of the new generation of low-power dynamic memory (Low Power DRAM), it provides lower power and higher-speed operation capabilities, thereby meeting the performance requirements required by today's high-speed systems. [0003] When performing a memory test, traditionally, a memory unit can generate an effective data window (Data Window) according to an external clock signal, and a memory tester obtains data for testing. However, the effective period of the data window is shortened with the improvement of the operating speed of the memory. Moreover, the delay time between the clock s...

AI Technical Summary

Problems solved by technology

However, as the memory operation speed increases, the effective period of the data window is shortened

And the delay time between the clock signal and the data signal channel (data output terminal) is relatively increased by the influence of temperature, volume and pressure (PVT for short)

As a result, the data window generated by the memory unit has an excessively large displacement error range during its data validity period

Therefore, it is difficult for the memory tester to correctly obtain the valid data contained in the shifted data window affected by the PVT, resulting in failure of the memory test.

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