A method and device for realizing frequency synchronization
A frequency synchronization and synchronization module technology, applied in synchronization devices, digital transmission systems, electrical components, etc., can solve the problems of different, poor PDV synchronization performance, and low synchronization accuracy.
Active Publication Date: 2020-02-14
ZTE CORP
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Problems solved by technology
[0005] In the existing method for realizing frequency synchronization, due to different forward and reverse traffic loads in the network or other reasons, the delay jitter (PDV, Packet Delay Variation) of the packet between the master device and the slave device and the slave device will be caused. The PDV to the master device is also different
If the forward PDV (that is, the PDV between the master device and the slave device) is large, and the reverse PDV (that is, the PDV between the slave device and the master device) is small, then only relying on T1 and T2 for frequency recovery, too much A large PDV can lead to poor synchronization performance, resulting in less accurate synchronization
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[0072] In order to facilitate the understanding of those skilled in the art, the present invention will be further described below in conjunction with the accompanying drawings, which cannot be used to limit the protection scope of the present invention. It should be noted that, in the case of no conflict, the embodiments in the present application and various manners in the embodiments can be combined with each other.
[0073] see figure 1 , the present invention proposes a method for realizing frequency synchronization, including:
[0074] Step 100: Obtain the delay jitter PDV and reverse PDV of the forward packet within a first preset time, and / or obtain the forward packet loss rate and reverse packet loss rate within the first preset time.
[0075] In this step, obtaining the forward packet loss rate and the reverse packet loss rate within the first preset time includes:
[0076] Obtain the serial number of each sync message received within the first preset time, and the...
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A frequency synchronization method and device. The method comprises: acquiring a packet delay variation (PDV) of a forward packet and a reverse PDV in a first preset time, and / or acquiring a forward packet loss rate and a reverse packet loss rate in the first preset time; determining that the acquired forward PDV and the reverse PDV meet the following formula: forward_delay_stheta > reverse_delay_stheta(1+a); or determining that the acquired forward packet loss rate is equal to the reverse packet loss rate, and the acquired forward PDV and the reverse PDV meet the following formula: forward_delay_stheta > reverse_delay_stheta(1+a); or determining that the forward packet loss rate is greater than the reverse packet loss rate, and performing frequency synchronization according to the time of transmitting a Delay_Req message and the time of receiving the Delay_Req message; wherein the forward_delay_stheta is the forward PDV, and the reverse_delay_stheta is the reverse PDV, and a is a preset value.
Description
technical field [0001] The invention relates to clock synchronization technology, in particular to a method and device for realizing frequency synchronization. Background technique [0002] The Institute of Electrical and Electronics Engineers (IEEE, Institute Electrical and Electronics Engineers) 1588v2 is a precision time synchronization protocol (PTP, Precision Time Protocol), which is a master-slave synchronization system. During the synchronization process of the system, the master device periodically releases time stamp information, and the slave device calculates the line time delay and master-slave time difference between the master device and the slave device according to the time stamp information received from the master device. The master-slave time difference adjusts the local time so that the time of the slave device maintains the same frequency and phase as that of the master device. IEEE1588 can realize frequency synchronization and time synchronization at t...
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IPC IPC(8): H04L7/00
CPCH04L7/00
Inventor 李春华
Owner ZTE CORP