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Incremental register retiming of an integrated circuit design

A circuit design, retiming technology, used in CAD circuit design, computer-aided design, instrumentation, etc.

Active Publication Date: 2017-03-15
ALTERA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such changes in IC design may require complete duplication of physical design operations and register retiming operations

Method used

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  • Incremental register retiming of an integrated circuit design
  • Incremental register retiming of an integrated circuit design
  • Incremental register retiming of an integrated circuit design

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0172] Additional embodiment 1: A method for operating a circuit design computing device, the method comprising: using the circuit design computing device, receiving a first circuit design and an implementation of the first circuit design generated at least in part as a result of a register retiming operation; using the circuit design computing device, receiving a second circuit design as a result of an engineering change order for the first circuit design; using the circuit design computing device, identifying differences between the first circuit design and the second circuit design; and using the circuit design computing device, performing a compilation of the second circuit design to generate a second circuit design implementation, wherein the compilation involves reconfiguring the register based on the identified differences between the first and second circuit designs and the register The result of a timed operation to perform an increment register retime operation.

Embodiment 2

[0173] Additional embodiment 2: The method of additional embodiment 1, wherein identifying the difference between the first circuit design and the second circuit design comprises: identifying a first region of the first circuit design having a predetermined function; and identifying a second region of the second circuit design having the same predetermined function.

Embodiment 3

[0174] Additional embodiment 3: The method of additional embodiment 2, further comprising: identifying a third region of the first circuit design coupled to the first region; and identifying a third region of the second circuit design coupled to the second region the fourth area.

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Abstract

The invention relates to an incremental register retiming of an integrated circuit design. A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design. For example, the circuit design computing equipment may preserve the register retiming solution from the first circuit design implementation for portions of the second circuit design that are outside the region-of-change and incrementally create graphs that allow to incrementally solve the register retiming problem during the second circuit design implementation.

Description

[0001] This application claims priority to US Patent Application No. 14 / 846,645 filed September 4, 2015, which is hereby incorporated by reference in its entirety. technical field [0002] The present application relates to integrated circuits, and more particularly to performing incremental register retiming for integrated circuit designs. Background technique [0003] Each transition from one technology node to the next has resulted in smaller transistor geometries and thus potentially more functionality per integrated circuit area. Synchronous integrated circuits have further benefited from this development as evidenced by reduced interconnect and cell delays which have resulted in increased performance. [0004] To further increase performance, schemes have been proposed, such as register retiming, in which registers are moved between combinatorial logic sections, thereby achieving a more even distribution of delays between registers, and thus enabling integrated circuit...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/3312G06F30/398G06F30/39G06F30/33G06F30/34G06F2119/12G06F30/392
Inventor N·辛纳杜莱G·R·邱
Owner ALTERA CORP
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