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Etching method of interlayer dielectric layer and its inner contact hole

A technology of interlayer dielectric layer and contact hole etching, which is applied in semiconductor/solid-state device components, semiconductor devices, electrical components, etc., and can solve problems such as device leakage

Active Publication Date: 2019-07-23
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Based on this, it is necessary to provide a new etching method for the interlayer dielectric layer and the contact hole in the layer to solve the problem of device leakage caused by overetching of the contact hole.

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  • Etching method of interlayer dielectric layer and its inner contact hole
  • Etching method of interlayer dielectric layer and its inner contact hole
  • Etching method of interlayer dielectric layer and its inner contact hole

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Embodiment Construction

[0027] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the associated drawings. A preferred embodiment of the invention is shown in the drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] The in...

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Abstract

The invention relates to an interlayer dielectric layer, and an etching method of contacts in the interlayer dielectric layer. For the etching method of contacts in the interlayer dielectric layer, a double etching barrier layer structure is used, so that the etching progress difference in each area, with different thickness, of an ILD layer, can be reduced, and the etching progress difference in the areas with different thickness can be greatly reduced. The etching method of contacts in the interlayer dielectric layer improves the uniformity of etching, prevents the barrier layer of the too thin area of an oxide-film layer from cutting through and from too early over etching by STI, and avoids failure of a chip because of electric leakage.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an etching method for an interlayer dielectric layer and a contact hole in the layer thereof. Background technique [0002] In the chip manufacturing process, contact hole etching is a very important process step. In this step, contact holes are etched in the interlayer dielectric (ILD) layer, and then metal is filled in the contact holes to realize the bottom device and Connection between metal wires. Wherein the ILD includes a multi-layer film, and the thickness of each layer is different. [0003] figure 1 It is a traditional ILD layer structure diagram, and the ILD layer includes a multi-layer film: a first silicon oxide dielectric layer 110, a second silicon oxide dielectric layer 130, a borophosphosilicate glass (BPSG) layer 140, a polysilicon layer 150 and silicon oxynitride (SION) dielectric layer 200 . After the ILD undergoes chemical mechanical polishing (...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/311H01L23/522
Inventor 李健
Owner CSMC TECH FAB2 CO LTD