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Digital clock-duty-cycle correction

A duty cycle correction and duty cycle technology, applied in pulse duration/width modulation, pulse technology, pulse processing, etc., can solve the problems of circuit duty cycle distortion, difficulty in maintaining duty cycle, and circuit failure

Active Publication Date: 2017-05-10
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, a circuit that relies on two clock edges may not function correctly if a 50% duty cycle clock is not applied to the circuit
Unfortunately, many types of circuits distort the duty cycle, and it can be difficult to maintain a 50% duty cycle

Method used

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  • Digital clock-duty-cycle correction
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  • Digital clock-duty-cycle correction

Examples

Experimental program
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Embodiment Construction

[0012] Certain terms are used throughout the following description and appended claims to refer to particular system components. Those skilled in the art will appreciate that different companies may refer to differently named components. This article does not intend to distinguish between components with different names, but to distinguish components by function. In the discussion below and in the scope of the claims, the terms "include" and "comprises" are used in an open sense and should therefore be interpreted to mean "including but not limited to...". Also, the term "couple / couples" is intended to refer to an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The expression "based on" is intended to mean "based at least in part on". Thus, if X is based on Y, X can be based on Y and any number of other ...

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PUM

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Abstract

The invention relates to digital clock-duty-cycle correction. A clock generator includes a duty cycle correction circuit. The duty cycle correction circuit includes a duty cycle detector. The duty cycle detector, includes a first programmable delay element (112) and a controller (114). The first programmable delay element (112) is configured to delay a clock signal. The controller (114) is configured to vary an amount of delay applied to the clock signal by the first programmable delay element (112), and to apply a delayed version of the clock signal, provided by the first programmable delay element (112), to locate an edge of a different version of the clock signal and measure time during which the different version of the clock is high. The controller (114) is also configured to generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on measured time during which the different version of the clock is high.

Description

Background technique [0001] Clock signals are often used in many electronic circuits and for various purposes. For example, clock signals are used to trigger synchronous circuits (eg, flip-flops) in digital circuits (such as processors, memory devices, etc.). Clock signals can be generated using various types of oscillators and supporting circuitry. The clock signal continuously transitions between two levels (eg, logic high and logic low). The clock signal has a duty cycle determined by periods of logic high and periods of logic low. [0002] The duty cycle of a clock signal is usually expressed as a percentage. For example, a clock signal with a pattern of 80% high and 20% low has a duty cycle of 80%. In some applications, it may be desirable for the clock signal to have a duty cycle of 50% duty cycle, where the 50% duty cycle has equal high and low portions of the waveform. For example, a circuit that relies on two clock edges may not function correctly if a 50% duty c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/017
CPCH03K3/017H03K5/1565H03K7/08
Inventor M·艾尔布德里
Owner TEXAS INSTR INC