Chip automatic test method and system

Abstract

The invention relates to an automatic chip testing method and an automatic chip testing system. The automatic chip testing method includes recording testing values of all pins at all testing time points of a tested chip in real time; extracting the testing values; comparing the testing values with expectation values and generating a comparison report according to a comparison result; positioning failure information of the tested chip according to the comparison report, wherein the failure information includes failure pins and failure time points of the failure pins. The automatic chip testing method is capable of acquiring all the failure time points of all the failure pins, facilitating positioning analysis of failure positions and failure reasons according to the failure time points of the failure pins, analyzing the testing values comprehensively through setting of different expectation values and offering more detailed and accurate testing results to guarantee the testing success rate.

Description

technical field [0001] The invention relates to the field of chip manufacturing and testing, in particular to a chip automatic testing method and system. Background technique [0002] Chip automatic test system is also called ATE, ATE mainly includes hardware circuit and operating software. The hardware circuit is only the basis for automatic testing, and it needs to be used in conjunction with the operating software to realize the automatic testing function, including the communication protocol with the probe station Prober and the manipulator Handler, the real-time display of online testing of test items, yield statistics, data log storage, Product programming function interface, engineering debugging, etc. can be used for actual mass production automation testing. [0003] In the traditional technology, the ATE operating software pre-sets the expected value (ie Output value) of each pin of the chip under test at multiple test time points in a certain memory (RAM). Once t...

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Problems solved by technology

[0003] In the traditional technology, the ATE operating software pre-sets the expected value (ie Output value) of each pin of the chip under test at multiple test time points in a certain memory (RAM). Once the hardware circuit determines that a certain value of the chip under test The output value vector of each pin does not match the corresponding expected value in the memory, and the corresponding flag is immediately set to the invalid state, and the operating software reads the flag and feeds back the measurement result, that is, in the traditional technology, only a limited capacity can be viewed failure pins, it is impossible to conduct a comprehensive chip test failure analysis based on the limited capacity of failure pins

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