A Design Method of High Performance Inexact Redundant Binary Multiplier

Abstract

The invention discloses a high-performance non-precision redundant binary multiplier and a design method thereof; the high-performance non-precision redundant binary multiplier is composed of a non-precision Booth encoding unit, a precision Booth encoding unit, a non-precision redundant binary 4-2 compressor unit, a precision redundant binary 4-2 compressor unit, a precision compression tree structural unit and a redundant binary digital number-to-common binary number conversion unit, wherein H bit high-order of a product of the non-precision redundant binary multiplier is acquired by using the precision Booth encoding unit and the precision redundant 4-2 compressor unit, and L bit low-order of the product is acquired by using the non-precision Booth encoding unit and the non-precision redundant 4-2 compressor unit. The high-performance non-precision redundant binary multiplier is high in speed, low in power consumption and small in area, and has a promising prospect in the fields of real-time embedded processing and other low-power-consumption digital circuits.

Description

Technical field: [0001] The invention relates to the field of inaccurate circuit design, in particular to a high-performance inaccurate redundant binary multiplier and a design method thereof. Background technique: [0002] With the continuous enrichment and development of the functional experience of various mobile device terminals, power consumption has become a key issue restricting the development of digital integrated circuit design. The industry's requirements for chip design have changed from pursuing high performance and small area to comprehensive requirements for performance, area and power consumption. [0003] A large number of studies have shown that the calculation accuracy of digital integrated circuits is directly proportional to the power consumption. Reducing the calculation accuracy can achieve the effect of reducing power consumption. At the same time, this energy saving and power consumption reduction are very obvious. The method and design concept of a...

AI Technical Summary

Problems solved by technology

[0004] Existing precise multipliers are faced with increasingly stringent requirements for real-time and low-power computing. Currently, existing ordinary binary non-precise multipliers still need precise compression in the process of high-order partial product compression, so there is still a problem of continuous carry. This is not conducive to the design of high-speed parallel multipliers, and it is urgent to design new high-speed parallel inaccurate multipliers to further improve performance and reduce power consumption

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