SSD master control Buffer, SSD master control and SSD unaligned write data transmission control method

A technology for data transmission and data writing, applied in electrical digital data processing, instruments, etc., can solve the problem of occupying a lot of CPU time and resources, and achieve the effect of improving capacity, reducing invalid waiting time, and improving DMA transmission efficiency.

Active Publication Date: 2017-05-31
HUNAN GOKE MICROELECTRONICS
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0021] The technical problem to be solved by the present invention is to provide a SSD master control Buffer, SSD master control and SSD non-aligned write data transmission control method to solve the problem that the existing non-aligned write method takes up more CPU time resources. , The problem of low transmission efficiency between DMAs, improve the efficiency of data transmission between DMAs, reduce invalid waiting, and finally improve SSD data throughput

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  • SSD master control Buffer, SSD master control and SSD unaligned write data transmission control method
  • SSD master control Buffer, SSD master control and SSD unaligned write data transmission control method
  • SSD master control Buffer, SSD master control and SSD unaligned write data transmission control method

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Embodiment Construction

[0043] The present invention scheme such as image 3 shown. The biggest difference between it and the prior art is that there are two more hardware modules, WD flag and RD flag.

[0044] WD Flag (Write DMA Flag) definition: According to the SSD front-end protocol, the SSD transmission data must be sector-aligned, and the size of each sector is 512B. Therefore, in this scheme, it is stipulated that each sector space in the Buffer has its own 1-bit information corresponding to it in WDFlag. The WD Flag of a certain sector space is 0, indicating that the Write DMA can write the sector space; if its WD Flash is set to 1, it indicates that the sector space is filled by the Write DMA or reserves space for the Read DMA to write data.

[0045] RD Flag (Read DMA Flag) definition: According to the SSD front-end protocol, SSD transmission data must be sector-aligned, and the size of each sector is 512B. Therefore, in this scheme, it is stipulated that each sector space in Buffer has i...

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Abstract

The invention discloses an SSD master control Buffer, SSD master control and an SSD unaligned write data transmission control method. In a whole read filling process, a CPU only participates in one step, and buffer application, data synchronization and buffer release are completed automatically by logics according to data transmission control rules, so that the ability of the CPU to process other events is improved. In the method, once Read DMA completes write of data of part 2 and part 3, RD flags where the part 2 and the part 3 are located are set, and even if data of part 1 are not ready, the Read DMA still executes read operation on part 1+ part 2 + part 3 immediately, so that Read DMA waiting time is shortened greatly, and DMA intertransmission efficiency is improved effectively.

Description

technical field [0001] The invention relates to the field of SSD data reading and writing, in particular to a SSD master control buffer, SSD master control and SSD non-aligned write data transmission control method. Background technique [0002] In the mainstream SSD master control, the front end must read and write data according to the sector (512Byte) length data alignment, while the SSD often uses the unit (unit size is 4KByte or 8KByte) alignment to flush data and check table entries for convenient management. Unaligned write refers to the write behavior that the range of read and write data is not aligned according to the unit, such as figure 1 shown. exist figure 1 In the scenario, it is necessary to fill in the unaligned part (yellow area) through a read operation. This filling operation is called read filling. After completing the filling, the data is downloaded to the flash and the table is changed. [0003] to combine figure 1 , figure 2 The existing methods...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28
CPCG06F13/28G06F2213/2806
Inventor 李雷陈旭光杨万云周士兵彭鹏马翼田达海
Owner HUNAN GOKE MICROELECTRONICS
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