Standard Cell Library Timing Test Circuit Layout Structure and Layout Method

Abstract

The invention relates to a standard unit library timing sequence test circuit layout structure and layout method. A timing sequence test circuit is composed of an even number of standard units, the standard units stored in a standard unit library have fixed lengths and widths, all standard units in the whole timing sequence test circuit are arranged inside an S-shaped loop structure in which the standard units are connected at heads and tails and are symmetrical up and down. Compared with the simple rectangular or square circuit layout, the problems that the number of the standard units is increased and a test ring is horizontally tensioned are solved, convergence of the shape of the test ring is realized, convenience is provided for the placement of a top layer circuit, meanwhile the layout design is optimized, the utilization rate of the layout space is improved, and with the increase of the number of the standard units, the advantages will be more obvious; and compared with the single-margin S-shaped circuit layout, the structure has the advantages that the problem that the interconnecting line between the standard units at the head and the tail is too long is solved, the influence of the interconnecting line is reduced, and the timing sequence test is more accurate. The idea of combining the structural optimization algorithm structure with the Cadence software facilitates the layout and wiring, and improves the working efficiency.

Description

technical field [0001] The invention relates to a circuit layout structure, in particular to a standard cell library timing test circuit layout structure and a layout method. Background technique [0002] With the continuous development of integrated circuit design and manufacturing technology, the design method based on the standard cell library in digital integrated circuits is gradually becoming standardized, and has been widely used in the design process of various application-specific integrated circuits. As the feature size of the process reaches the nanometer level, and the delay time of a single transistor is shortened to picoseconds, integrated circuit designers need more accurate delay parameters in order to better reserve margins in the initial design to prevent due to residual delays. Insufficient quantity causes rework and waste caused by excessive surplus. These put forward higher requirements for the test accuracy of the standard cell library, and how to eval...

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Problems solved by technology

[0004] The present invention aims at the problems of high interconnection difficulty, waste of layout resources, and length of interconnection lines between units in the traditional ring structure circuit layout, and proposes a standard unit library timing test circuit layout structure and layout method, a symmetrical S-shaped ring Road structure, which has the advantages of optimizing layout design, improving layout space utilization, reducing the impact of interconnection, etc., and can also alleviate the problem of top-level placement

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