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A kind of asynchronous set d flip-flop resistant to single event upset

An anti-single event and trigger technology, applied in the direction of reliability improvement modification, pulse technology, logic circuit, etc., can solve the problem of low anti-single event flipping ability, and achieve the effect of improving the anti-single event flipping ability

Active Publication Date: 2020-03-24
SHENZHEN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] An embodiment of the present invention provides an asynchronously set D flip-flop that is resistant to single-event upset, aiming to solve the problem that the anti-single-event upset capability of the asynchronously set D flip-flop is not high in the prior art

Method used

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  • A kind of asynchronous set d flip-flop resistant to single event upset
  • A kind of asynchronous set d flip-flop resistant to single event upset
  • A kind of asynchronous set d flip-flop resistant to single event upset

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Embodiment Construction

[0023] In order to make the purpose, features, and advantages of the embodiments of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, The described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present invention.

[0024] see figure 1 , figure 1 It is a schematic diagram of the circuit structure of the C unit circuit based on the DICE structure, and the C unit circuit based on the DICE structure includes:

[0025] A first signal input terminal IN1, a second signal input terminal IN2, a signal output terminal OUT, a P-channel MOS transistor MP1, a P-...

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Abstract

The invention belongs to the technical field of D flip-flops, and provides an asynchronous set D flip-flop with the capacity for resisting single event upset. The D flip-flop comprises a clock signal input circuit, a reset signal input circuit, a main latch buffering circuit, an auxiliary latch buffering circuit, a main latch and an auxiliary latch, and the main latch and the auxiliary latch are latches with bimodule redundancy reinforcing. Compared with the prior art, the buffering circuits are additionally arranged before the main latch and the auxiliary latch, the capacity for resisting single event upset of the asynchronous reset D flip-flop is improved, bimodule redundancy reinforcing is carried out on the main latch and the auxiliary latch, namely the main latch and the auxiliary latch are separated into a pull-up PMOS tube and a pull-down NMOS tube redundant to each other in the C2MOS circuits, a feedback loop possibly caused by single particle transient pulse in the auxiliary latch is avoided, the C2MOS circuits in the main latch and the auxiliary latch are improved, control over the circuits by clock signals is achieved through a CMOS transmission gate, and the capacity for resisting single event upset of the asynchronous set D flip-flop is improved further.

Description

technical field [0001] The invention belongs to the technical field of D flip-flops, in particular to an asynchronously set D flip-flop resistant to single-event reversal. Background technique [0002] There are a large number of high-energy particles (protons, electrons, heavy ions, etc.) in the universe. After the sequential circuit in the integrated circuit is bombarded by these high-energy particles, the state it maintains may be reversed. This effect is called the single event reversal effect. The higher the LET (Linear Energy Transfer) value of the bombardment IC, the easier it is to produce single event upset effects. After the combined circuit in the integrated circuit is bombarded by these high-energy particles, it is possible to generate a transient electric pulse. This effect is called the single event transient effect. The higher the LET value of the single particle bombarding the integrated circuit, the longer the duration of the generated transient electric pul...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/003H03K3/356
CPCH03K3/356H03K19/00338
Inventor 贺威贺凌翔张准骆盛吴庆阳
Owner SHENZHEN UNIV
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