A single-event upset-resistant latch with low delay power product

Abstract

The invention discloses an anti-single-event-upset latch register with a low delay-power product. By use of a novel cross coupling structure capable of isolating an upset state, recovery of the upset state is accelerated through design of a reasonable negative feedback passage. In case of a data transparent mode, negative feedback is cut off so as to improve the writing speed of a circuit. A simulation result under a 40nm CMOS technology shows that the critical charge ratio of the latch register provided by the invention is more than 50 times higher than that of a conventional latch register. The delay-power product is only 0.0035fs*J, and the propagation time delay under the non-loaded condition is only 23.3ps, which is lower than that of a same-type latch register.

Description

【Technical field】 [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a novel anti-single event reversal latch with low delay power consumption product. 【Background technique】 [0002] With the advancement of integrated circuit manufacturing technology, the feature size of CMOS devices has reached the nanometer level, and the power supply voltage and node critical charge of digital circuits are also decreasing, making them more and more vulnerable to soft damage caused by single event effects (SEU). The effect of errors. Especially for a latch or flip-flop, once its internal node is affected by a single event, it will cause the latch state to flip, resulting in the destruction of the stored signal. Single event effects have become a major source of soft errors in digital integrated circuits. For digital memory chips used in special fields (aerospace, military industry, etc.), it is necessary to carry out anti-radiation h...

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Problems solved by technology

DICElatch proposed by T.Calin and M.Nicolaids (T.Calin, M.Nicolaids, R.Velazco, 1996, IEEE Transactions on Nuclear Science, 43, p2874.) has good anti-single event flipping ability, and the critical charge of its key nodes is much larger than that of traditional The latch, but requires a lot of hardware overhead, such as large-size transistors

FERSTlatch proposed by M.Fazeli and S.G.Miremadi et al. (M.Fazeli, S.G.Miremadi, A.Ejlali, A.Patooghy, 2009, Computers & Digital Techniques, 3, p289.) Its internal nodes have a good ability to resist single event effects, however , if the injected particle energy is strong enough, the external output node of the latch also has a great risk of flipping, and the circuit also has a large power consumption delay product and a certain hardware overhead

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