Semiconductor structures and methods of forming them

Abstract

The present invention discloses a semiconductor structure having a stop layer for a planarization process therein and a method of forming the same. The method includes the steps of: forming a trench in a substrate and between active regions; filling the trench with an isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; The annealed and doped isolation region was annealed and its planarization depth measured. The coefficients of thermal expansion (CTE) of the stop layer, the dielectric layer and the active region are different.

Description

technical field [0001] Embodiments of the invention relate to semiconductor structures and methods of forming the same. Background technique [0002] Semiconductor devices are used in numerous electronic devices such as computers, communications, consumer electronics, automobiles, and others. Semiconductor devices include integrated circuits (ICs) formed on semiconductor wafers by depositing various types of thin film materials over the semiconductor wafers and patterning the thin film materials to form integrated circuits. The most common active elements in ICs are transistors including planar field effect transistors (FETs) such as metal oxide semiconductor (MOS) transistors and 3D fin field effect transistors (FinFETs). [0003] In integrated circuits, trench isolation structures are often used to separate and isolate two active regions in a semiconductor device. The trench isolation structure is typically formed by recessing the substrate, overfilling it with a dielect...

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Problems solved by technology

However, it remains a challenge to precisely control the planarization depth and sufficiently maintain the structural stability between the trench isolation structure and adjacent structures.

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