Detection circuit and method of storage elements in FPGA (Field Programmable Gate Array) chip

Abstract

The invention provides a detection circuit and method of storage elements in an FPGA (Field Programmable Gate Array) chip. The circuit comprises slices, wherein each slice comprises a plurality of channels and each channel comprises a first element, a lookup table and a second element which are connected in sequence; each second element is connected with the first element of the next channel. When the elements receive a first clock signal, a detection signal is received and stored; when the elements receive a second clock signal, a reference signal is received and stored and a result is output. Or the circuit comprises a detected circuit and a detection circuit in two slices of a configurable logic block; the detected circuit is provided with a plurality of third elements to be detected and the detection circuit is provided with a plurality of channels for connecting the lookup tables and fourth elements; each fourth element is connected with input of the lookup table of the next channel; each third element is connected with the other input of the lookup table. The third elements are used for receiving and storing the detection signal and the lookup tables are used for receiving the reference and detection signals and outputting the reference and detection signals to the fourth elements; when the fourth elements receive a fourth clock signal, the detection signals are received and stored; when the fourth elements receive a fifth clock signal, the reference signal is received and stored and the result is output. The elements are storage elements.

Description

technical field [0001] The invention relates to the field of integrated circuit chip testing, in particular to a detection circuit and a detection method of a storage element in an SRAM FPGA chip. Background technique [0002] FPGA (Field-Programmable Gate Array), that is, field programmable gate array, is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. [0003] Xilinx 7 series FPGA includes Artix-7, Kentix-7 and Virtex-7 three subclasses. The configurable logic block (CLB) structure of the three types of devices is the same, such as figure 1 shown. Each CLB consists of 2 slices (SLICE), and each slice has a unique physical location number (such as X0Y0, X2Y1). [0004] Storage Element (Storage Element) is a functional module in FPGA SLICE that implements programmable sequential logic, and is a key unit for synchronous design, establishment of pipeline structure, and improvement of FPGA internal logic operation speed. The ...

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Problems solved by technology

[0008] The existing detection methods for storage components are all detection methods for Xilinx’s early Virtex, Virtex-II and other types of storage components. Since the structure of the CLB SLICE of the Virtex-7 series has been greatly improved,

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