mtp device and manufacturing method thereof

Abstract

The invention discloses an MTP device, comprising: the first to third NMOS transistors serving as selection transistors, storage transistors and word line transistors are all formed in a P well, the polysilicon gate of the second NMOS transistor in the middle is a polysilicon floating gate, The first extension end of the polysilicon floating gate forms a programming coupling structure, and the second extension end forms an erasing structure; the second extension end of the polysilicon floating gate spans the first active region composed of the first N well; the erasing structure also includes a second A P+ region and a first N+ region, and two implanted regions overlap each other on the first active region in a direction parallel to the second extension end of the polysilicon floating gate, and the size of the overlapping region depends on the first N+ region and the first active region. The overlay accuracy of the source area is determined, ensuring that the overlay structure that can be effectively erased can be realized under the condition that the overlay deviation is the largest. The invention also discloses a manufacturing method of the MTP device. The invention can improve the erasing efficiency of the device, and prevent the failure of MTP erasing and the problem of test failure caused by it.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a multi-time programmable (Multi-Time Programmable, MTP) device. The invention also relates to a manufacturing method of the MTP device. Background technique [0002] Such as figure 1 As shown, it is a top view structure diagram of an existing MTP device; including: [0003] A P well 101, a first N well 102, and a second N well 103 formed on a semiconductor substrate such as a silicon substrate, and three NMOS transistors are formed in the P well 101, namely NMOS transistors 201, 202 and 203, 3 The three NMOS transistors have polysilicon gates 1041, 1042 and 1043 respectively, and the three NMOS transistors include four N+ regions, which are respectively N+ regions 105a, 105b, 105c and 105d, wherein the N+ regions 105b and 105c are shared by two adjacent NMOS transistors . [0004] The polysilicon gate 1042 is a floating gate, that is, a polysilic...

AI Technical Summary

Problems solved by technology

[0009] The existing MTP has always had the problem of insufficient process margin (margin) for the overlay of the N+ area 105e to the active area (OD), which caused insufficient erasure (Erase) efficiency, resulting in the failure of related MTP tests

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