Chip package structure

Abstract

A chip package structure is provided. The chip package structure includes a redistribution substrate. The chip package structure includes a first chip structure over the redistribution substrate. Thechip package structure includes a first solder bump arranged between and electrically connecting the redistribution substrate and the first chip structure. The chip package structure includes a firstmolding layer surrounding the first chip structure. The first molding layer and the first chip structure are both spaced apart from the redistribution substrate by the first solder bump, thereby defining a gap there-between. The chip package structure includes a second chip structure over the first chip structure. The chip package structure includes a second molding layer surrounding the second chip structure. The chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump, and filled into the gap.

Description

technical field [0001] Embodiments of the present disclosure relate to semiconductor structures, and more particularly to chip packaging structures and methods for forming the same. Background technique [0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in integrated circuit materials and design have resulted in each generation of circuits being smaller and more complex than the previous generation. These advances, however, increase the complexity of the integrated circuit process. [0003] In the advancement of integrated circuits, functional density (the number of interconnected devices per unit chip area) has increased as geometry size (the smallest component or circuit that a process can produce) has shrunk. Advantages of the aforementioned downscaling processes are increased throughput and reduced associated costs. [0004] However, as the size of the structure continues to shrink, it will be more difficult to ...

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Problems solved by technology

[0004] However, as the size of the structure continues to shrink, it will be more difficult to process, and the process (such as thermal process) is more likely to affect the performance of the integrated circuit

In summary, the current challenge is to form smaller and smaller semiconductor devices with reliability

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