MLVDS-based (multipoint low voltage differential signal-based) multi-card communication system

Abstract

The invention discloses an MLVDS-based multi-card communication system. The MLVDS-based multi-card communication system comprises a first communication card and a plurality of second communication cards, the first communication card and the second communication cards are communicated with each other, and every communication card is composed of an FPGA (field programmable gate array) chip, a firstMLVDS chip and a second MLVDS chip; the first communication card also comprises a clock chip; the FPGA chip of the first communication card is connected with the clock chip and the second MLVDS chip of the first communication card, and the clock chip is connected with the first MLVDS chip of the first communication card; the FPGA chips of the second communication cards are connected with the firstMLVDS chips and the second MLVDS chips of the second communication cards respectively; the second MLVDS chip of the first communication card is connected with the second MLVDS chips of the second communication cards through a data bus, and the first MLVDS chip of the first communication card is connected with the first MLVDS chips of the second communication cards through a clock bus to achieve clock sharing between the first communication card and the second communication cards. The MLVDS-based multi-card communication system achieves high-speed communication among multiple cards through low-cost chips and an FPGA internal circuits.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to an MLVDS-based multi-board communication system. Background technique [0002] With the development of communication technology, the hardware part of the communication system is becoming more and more complex. The hardware part of most systems is composed of multiple boards. Multiple boards need to interact with data, and there is an increasing demand for high-speed, real-time transmission of large amounts of data between boards. Due to the control of system complexity and cost considerations, the communication between boards is generally connected through the bus. [0003] The current bus between boards is generally an asynchronous clock bus with a low transmission rate, and the rate can only reach several megabits per second. The physical layer of a few high-speed bus communication protocols requires interconnection between every two boards. Three or more boards cannot ...

AI Technical Summary

Problems solved by technology

The physical layer of a few high-speed bus communication protocols requires interconnection between every two boards. Three or more boards cannot share the bus, and special and expensive communication chips are required.

In this way, not only the connection is complicated, but also the function is single, the flexibility is low, the cost is high, and it cannot meet the diverse needs of users

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