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Leak location system and method for chip encryption design

A positioning system and chip technology, applied in computing, computer security devices, internal/peripheral computer component protection, etc., can solve the problems that chip designers cannot obtain security information, lack of high-level mask protection test systems, etc., and achieve cost The effect of low cost, perfect design and strong reliability

Active Publication Date: 2021-12-07
BEIJING SMARTCHIP MICROELECTRONICS TECH COMPANY +5
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] The existing chip design test has the following problems: 1. The chip test should be carried out after the board is released. If a problem is found in the design, it needs to be redesigned and printed. The chip designer cannot obtain security information during the chip design process. and leak points; 2. Lack of a test system for the design of high-level mask protection

Method used

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  • Leak location system and method for chip encryption design
  • Leak location system and method for chip encryption design

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Embodiment Construction

[0025] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0026]Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations thereof such as "includes" or "includes" and the like will be understood to include the stated elements or constituents, and not Other elements or other components are not excluded.

[0027] In order to help chip encryption designers to conduct security tests and obtain leak locations during the design process so as to better improve the design, this invention develops a leak location system for chip encryption design, which can detect leak points for various chip designs , has the characteristics of convenience, low cost, and timely feedback. The chip design is FPGA design or ASIC design. The present i...

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Abstract

The invention discloses a leak location system and method for chip encryption design, which are used for leak location of encryption chip design. The leak location system includes: an analysis module, an analysis module and a feedback module. The parsing module obtains the hierarchical structure and operation unit information of the actual hardware circuit by parsing the RTL file and the netlist file. The analysis module is electrically connected to the analysis module, and the analysis module analyzes the exact position of the leak point according to the hierarchical structure of the actual hardware circuit and the information of the operation unit, and calculates the success rate of the leak point location. The feedback module is electrically connected to the analysis module and the analysis module, and the feedback module compares the exact position of the leak point with the RTL file and the netlist file, and marks the leak point in the RTL file and the netlist file. The leak location system of the chip encryption design of the present invention can locate the leak point more precisely.

Description

technical field [0001] The present invention relates to the field of chip design. In particular, the present invention relates to a leak location system and method for chip encryption design. Background technique [0002] Today, the functionality and importance of encrypted devices is accepted for many applications. Since the hardware carrier of the encryption algorithm has higher security and efficiency than the software form, it has been designated as an essential security protection platform and encryption form by many industries. The hardware carrier includes cryptographic chips, smart cards, etc. [0003] Traditionally, the security of an encryption device is determined by the cryptographic algorithm used, the authentication method, and the mathematical complexity of the security protocol. However, for a practical encryption device, its security is not only related to the adopted cryptographic algorithm, but also involves aspects such as program implementation and har...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F21/71G06F21/55G06F11/36
CPCG06F11/366G06F21/556G06F21/71
Inventor 胡晓波唐明赵东艳张海峰唐晓柯原义栋李娜李延斌李煜光刘亮甘杰涂因子安春香邓剑伟何旭杰
Owner BEIJING SMARTCHIP MICROELECTRONICS TECH COMPANY