A Multiple Graphical Method

Abstract

The invention discloses a multi-time graphical method. The multi-time graphical method comprises steps that S01, a silicon center line pattern is formed on a substrate; S02, an oxide layer is deposited on the surface of the substrate, and the oxide layer is etched to form oxide sidewalls on both sides of the silicon center line pattern; S03, a first pattern layer is deposited on the bottom surfaceof the substrate, and the first pattern layer is etched to form first patterns on both sides of the oxide sidewalls; S04, a planarization material layer is deposited on the surface of the substrate,and etching is carried out to expose a silicon center line pattern; S05, the silicon center line pattern is removed, a second pattern layer is deposited on the surface of the substrate, and the secondpattern layer is etched to form second patterns on both sides of the oxide sidewalls; and S06, the planarization material layer and the oxide sidewalls are sequentially removed to form multiple graphical patterns in which the first patterns and the second patterns are alternated. The method is advantaged in that through combination of one-time lithography and the multi-time sidewall technology, the ultra-small pitch pattern is made in combination with the planarization technology.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a multiple patterning method. Background technique [0002] With the development of semiconductor technology, silicon semiconductor devices have undergone a transition from planar MOS devices to three-dimensional MOS devices (FinFETs), and the feature size of silicon fins (Fin) has been continuously reduced. In the 14nm generation technology, the pitch of the silicon fin layer pattern is only 48nm, and in the future 7nm process generation, the pitch of the silicon fin layer will be further reduced, and the most advanced 193i lithography machine can process such a small pitch pattern Nothing can be done. [0003] The existing FinFET process adopts a self-aligned double patterning (self-align double patterning, SADP) method to make the pattern of the silicon fin layer, and the method in the prior art cannot effectively control the space between the final formed sid...

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Problems solved by technology

[0003] The existing FinFET process adopts a self-aligned double patterning (self-align double patterning, SADP) method to make the pattern of the silicon fin layer, and the method in the prior art cannot effectively control the space between the final formed sidewalls. distance, and the line width of the finally formed graphics is consistent, there is no possibility of forming two line width graphics

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