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Layout Data Check Allocation Method

A technology of layout data and distribution method, which is applied in electrical digital data processing, special data processing applications, instruments, etc., and can solve the problems of long operation time and slow speed of physical layout data.

Active Publication Date: 2022-05-20
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a layout data inspection and distribution method to solve the problem of too long operation time and slow speed in processing and checking large-scale physical layout data in the prior art

Method used

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Embodiment Construction

[0019] The present invention realizes a method for parallel inspection of layouts. This method is different from the previous method of sequential inspection of layouts, but estimates the loading coefficient of the layers, and distributes the layers to Different distributed processors perform checks and combine them at the end, which greatly improves the speed of checking large-scale physical layout data, and solves the problem of long operation time and slow speed of processing and checking large-scale physical layout data in the prior art.

[0020] The difference between the present invention and the traditional method is that the loading factor (loading) of the estimated level is calculated, and the level is distributed to different distributed processors for inspection by calculating the number of graphics and calculation coefficients.

[0021] Step 1, extract information of each level in the layout. The information includes the number, name, and physical meaning of the la...

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Abstract

The invention discloses a layout data inspection distribution method, which comprises the following steps: Step 1, extracting information of each level in the layout; Step 2, calculating the number of polygonal figures in each level; Step 3, calculating the calculation formula for checking design rules The coefficient of the level; Step 4, calculate the loading coefficient of the level according to the number of graphics and the coefficient; Step 5, assign the level to different distributed processors for inspection according to the loading coefficient. The invention solves the problems of too long operation time and slow speed for processing and checking large-scale physical layout data in the prior art.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a method for checking and distributing layout data. Background technique [0002] In the field of integrated circuit manufacturing, manufacturers have established hierarchical design rules for each critical dimension of integrated circuit manufacturing process, including layer number, layer name, and physical meaning of the layer. IC designers need to strictly abide by the hierarchical design rules of IC manufacturers when designing and developing layouts. When the integrated circuit designer transmits the layout data to the integrated circuit manufacturer, it is also necessary to attach a layer information table, which includes the layer number, layer name, and physical meaning of the layer used in the layout data. [0003] As the design rules become smaller and smaller, some auxiliary technologies have also emerged. At present, one of the most important steps be...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/398
CPCG06F30/398
Inventor 张兴洲张燕荣
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP