A gate scanning drive circuit
A driving circuit and gate scanning technology, applied in static indicators, instruments, etc., can solve problems such as instability, reduced circuit reliability, and poor functionality, and achieve the effect of narrowing the border and avoiding circuit failure
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Embodiment 1
[0096] Such as Figure 7 Shown is a circuit diagram of Embodiment 1 of a gate scanning drive circuit. The nth level drive circuit unit includes a positive and negative scan control module 01, a pull-up module 02, a touch auxiliary module 03, a maintenance auxiliary module 04, and a memory compensation module 05 and the first capacitor C1. The positive and negative scan control module 01, the pull-up module 02, the maintenance auxiliary module 04 and the memory compensation module 05 are connected to the pull-up control node netAn; Lower the level VSS; the pull-up module 02 and the touch auxiliary module 03 are connected to the gate scanning signal line of the current stage, and the gate scanning signal line outputs the gate scanning signal Gn; the first capacitor C1 is connected to the pull-up control node netAn and Between the gate scanning signal lines of this stage.
[0097] Such as Figure 7 As shown, specifically, the pull-down sub-module 05A of the nth-level drive cir...
Embodiment 2
[0133] Figure 9 It is a schematic circuit diagram of Embodiment 2 of a gate scanning driving circuit of the present invention. The second embodiment is improved on the basis of the first embodiment, and the specific improvements are as follows:
[0134] 1. The memory compensation module 05 of the nth level drive circuit unit also includes a sixteenth thin film transistor M9B, the control terminal of the sixteenth thin film transistor M9B inputs the second clock signal CKm+4, and the two channels of the sixteenth thin film transistor M9B The terminals are respectively connected to the pull-up control node netAn and the input constant-voltage low-level VSS; the sixteenth thin film transistor M9B is responsible for clearing and resetting the memory compensation node netCn in time to ensure that the memory compensation node netCn can maintain synchronization with the pull-up control node netAn;
[0135] 2. The control end of the fourth thin film transistor M4 in the memory compe...
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