A high-speed cache device and a data high-speed read-write terminal

Abstract

This application discloses a high-speed cache device composed of a processor motherboard, DDR SDRAM and QDR SRAM. The QDR SRAM obtained by encapsulating QDR SRAM particles based on the DIMM interface adopted by conventional DDR SDRAM can directly communicate with the existing DIMM interface of the processor. The processor motherboard establishes a connection, because the difference in random address access efficiency between QDR SRAM and DDR SDRAM is not directly related to the interface type, and will not affect the high access efficiency characteristics of QDR SRAM, and because there is no need to replace The interface type on the main board of the device can bring higher access efficiency with a lower degree of modification, and meet the needs of special application scenarios such as banks. The present application also discloses a high-speed data read-write terminal provided with the cache device at the same time, which has the above-mentioned beneficial effects.

Description

technical field [0001] The present application relates to the field of data storage hardware, in particular to a high-speed cache device and a high-speed data read-write terminal. Background technique [0002] As is well known to the public, a data terminal usually includes a motherboard integrated with a processor and a separate data storage device, and there are also some on-chip registers on the motherboard for temporarily storing some data, but the storage capacity of these on-chip registers Smaller, when more data needs to be stored, an off-chip storage unit with a larger storage capacity is required. This application only discusses the situation when the off-chip storage unit is a memory with a fast data read and write speed and used for caching data. [0003] In most cases, SDRAM (Synchronous Dynamic Random Access Memory, Synchronous Dynamic Random Access Memory) is selected as the off-chip storage unit. Synchronization in SDRAM means that the clock needs to be synch...

AI Technical Summary

Problems solved by technology

Higher performance, can achieve 100% efficiency for random address access, but small capacity, low integration; while the QDR SRAM obtained by QDR (Quad Data Rate Static, quadruple rate) has two independent data channels, Data read / write operations can be performed at the same time, which belongs to the full-duplex working mode, with high random access rate and low read and write delay

[0005] However, QDR SRAM is only a standard. During the standard formulation process, it was given an interface packaging method different from DDR SDRAM, that is to say, its slot on the processor motherboard is also different from DDR SDRAM DIMM, resulting in the original processor The motherboard is not compatible with memory such as QDR SRAM. If you directly replace the processor motherboard based on the QDR SRAM interface, it will undoubtedly bring higher implementation costs.

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