Memory structure and manufacturing method thereof

Abstract

The present application discloses a memory structure and a manufacturing method thereof. The manufacturing method includes: doping a semiconductor substrate to form a first doped region and a second doped region; forming a first doped region on the first surface of the semiconductor substrate. An array stack, the first array stack has a plurality of first memory cells, each first memory cell includes a first gate conductor and a part of a first channel pillar; a conductive channel; and forming a second array stack on the second surface of the semiconductor substrate, the second array stack has a plurality of second memory cells, each second memory cell includes a second gate conductor and a second trench A part of the channel column, the second channel column and the first channel column are electrically connected through corresponding conductive channels, wherein the first doped region and the second doped region adopt the doping of the first type and the doping of the second type respectively. Doping, the two are opposite to form a PN junction.

Description

technical field [0001] The present invention relates to the field of memory, and more particularly, to a memory structure and a manufacturing method thereof. Background technique [0002] Nowadays, people pay more and more attention to highly integrated electronic devices, and high-speed, low-power, high-density semiconductor storage devices have been rapidly developed. 3D NAND is an emerging flash memory developed by the industry. It solves the limitations of 2D or planar NAND flash memory by vertically stacking multi-layer data storage units, and has higher precision, effectively reducing manufacturing costs and performance. consumption. [0003] However, in the current 3D NAND memory manufacturing process, the channel column connection between the array stacks will form an "L"-shaped structure due to process problems. The mobility decreases, thereby affecting the P / E (program / erase) performance of memory cells and even memory arrays. [0004] In addition, the array sta...

AI Technical Summary

Problems solved by technology

[0003] However, in the current 3D NAND memory manufacturing process, the channel column connection between the array stacks will form an "L"-shaped structure due to process problems. Decreased mobility, which affects the P / E (program / erase) performance of memory cells and even memory arrays

[0004] In addition, the array stacks cannot be fully aligned (Overlay Shift), and when the OSONO (Oxide-Silicon-Oxide-Nitride-Oxide) drilling process is performed at the bottom of the trench, it will cause damage to the channel pillars, which will seriously affect the memory. production yield

Images