A memory structure and a manufacturing method thereof

Abstract

A memory structure and a manufacturing method thereof are disclosed. The manufacturing method includes: doping a semiconductor substrate to form a first doped region and a second doped region; Forminga first array stack on a first surface of the semiconductor substrate, the first array stack having a plurality of first memory cells, each first memory cell including a first gate conductor and a portion of a first channel post; Forming a plurality of conductive channels spaced apart from each other in the semiconductor substrate; And forming a second array stack on the second surface of the semiconductor substrate, A second array stack has a plurality of second memory cells, Each of the second memory cells includes a second gate conductor and a portion of a second channel post electricallyconnected to the first channel post through a corresponding conductive channel, wherein the first doped region and the second doped region are doped with a first type of doping and a second type of doping, respectively, opposite to each other, thereby forming a PN junction.

Description

technical field [0001] The present invention relates to the field of memory, and more particularly, to a memory structure and a manufacturing method thereof. Background technique [0002] Nowadays, people pay more and more attention to highly integrated electronic devices, and high-speed, low-power, high-density semiconductor storage devices have been rapidly developed. 3D NAND is an emerging flash memory developed by the industry. It solves the limitations of 2D or planar NAND flash memory by vertically stacking multi-layer data storage units, and has higher precision, effectively reducing manufacturing costs and performance. consumption. [0003] However, in the current 3D NAND memory manufacturing process, the channel column connection between the array stacks will form an "L"-shaped structure due to process problems. The mobility decreases, thereby affecting the P / E (program / erase) performance of memory cells and even memory arrays. [0004] In addition, the array sta...

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Problems solved by technology

[0003] However, in the current 3D NAND memory manufacturing process, the channel column connection between the array stacks will form an "L"-shaped structure due to process problems. Decreased mobility, which affects the P / E (program / erase) performance of memory cells and even memory arrays

[0004] In addition, the array stacks cannot be fully aligned (Overlay Shift), and when the OSONO (Oxide-Silicon-Oxide-Nitride-Oxide) drilling process is performed at the bottom of the trench, it will cause damage to the channel pillars, which will seriously affect the memory. production yield

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