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A decoder and a method for implementing the same

A decoder and iterative decoding technology, applied in the direction of encoding, code conversion, encoding components, etc., can solve problems such as display, achieve the effect of storage optimization, reduce memory requirements, and save implementation costs

Active Publication Date: 2022-08-09
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0018] The check matrix H is the most important parameter in the entire encoding and decoding system. The check matrix H determines the anti-error performance of the entire encoding and decoding system. Although the anti-error performance is not reflected in the above encoding process, it is in the decoding process will appear

Method used

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  • A decoder and a method for implementing the same
  • A decoder and a method for implementing the same
  • A decoder and a method for implementing the same

Examples

Experimental program
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Effect test

no. 1 example

[0165] The first embodiment takes a simple random check matrix H as an example to describe the decoding process of the present invention. The check matrix H is:

[0166] Assuming that in the ith iteration, the decoding of the first column has been completed, and the decoding of the second column is about to be performed. According to the form of the check matrix H, two related check messages need to be solved: and These two formulas are based on Figure 4 Step 400 in the solution can be solved. below to solve As an example, the specific calculation process of step 400 is described in detail:

[0167] calculate The absolute value of :

[0168] calculate symbol: Positive numbers and zeros are represented by 0, and negative numbers are represented by 1;

[0169] in the above formula All are the values ​​recorded in the maintained verification message table. Here, only the verification message table can be queried according to the verification formula No. 3. ...

no. 2 example

[0186] The second embodiment, this embodiment shows the embodiment of the present invention after the decoding calculation is completed and compressed back to the compression table, FIG. 5(a) is a schematic diagram of storage after decoding and calculation in the related art, and FIG. 5(b) is this The storage schematic diagram after decoding and calculation in the embodiment of the invention, as shown in Figure 5(b), the calculation of the check message CR in each iteration of the present invention is only to extract the corresponding value from the compressed check information table, and The comparison operation does not need to be performed, but the comparison operation is not omitted. In the calculation of the compressed storage after the final variable message VR is calculated, the comparison operation still needs to be performed, but the storage and addressing involved have been determined by the relevant technology. A single point that is separated in , becomes a whole bl...

no. 3 example

[0188] The third embodiment, this embodiment provides an example of using the shuffled BP property to perform parallel operations. Since the calculation of a column of variable messages requires multiple verification messages, in this embodiment, it is assumed that the verification messages corresponding to different verification equations are stored in different single-port RAMs before the parallel calculation of these verification messages is performed to make To the purpose of reading data from different addresses at the same time. like Image 6 As shown, the box on the right shows the relationship between a variable (column) indicated by the exponential matrix of a QC-LDPC and two check equations (rows). To solve the two corresponding variable messages of the variable, it is necessary to obtain 2 corresponding check messages, these 2 check messages passed Image 6The parity message compression tables shown on the left stored in different RAMs are given simultaneously. I...

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Abstract

The invention discloses a decoder and a method for realizing decoding. The decoder at least comprises: a buffer unit for buffering received codewords from a channel; a storage unit for storing the compressed check message in a a check message compression table, used to transfer iteration information between two iterations; a calculation unit, used to initialize the check message by using the buffered received codeword in the initial state of the decoder; The verification message in the unit is converted into a variable message, and the calculation of iterative decoding is completed according to the obtained variable message and the buffered received codeword. When the calculated total variable message is invalid, the calculated variable message is converted into compressed Format check message; and when the calculated total variable message is invalid, continue the calculation of iterative decoding. The present invention compresses the memory scale requirement in the traditional similar design, and saves the realization cost due to the reduction of the memory requirement.

Description

technical field [0001] The present invention relates to, but is not limited to, encoding and decoding technologies, and particularly, to a decoder and a method for implementing decoding thereof. Background technique [0002] General communication systems such as figure 1 As shown, on the transmitting side, it can be divided into the following parts according to the processing flow: signal source processing, bit domain processing, symbol domain processing, and transmitting circuit; on the receiving side, processing is performed in the opposite direction to the above. [0003] In the field of channel coding, there are mainly two coding methods, one is convolutional code and the other is linear block code. For a long time, convolutional codes have been widely used due to their simple structure and acceptable performance, while traditional linear block codes, such as BCH codes, Reed-solomon codes, etc., have been widely used under the same hardware conditions. The performance ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11H04L1/00
CPCH03M13/1105H03M13/1148H04L1/0061
Inventor 白栎旸程晨孙远航李彧
Owner SANECHIPS TECH CO LTD
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