Non-volatile memory with restricted dimensions

Abstract

The invention relates to a non-volatile memory with restricted dimensions. A memory device includes a memory plane including a succession of neighboring semiconductor recesses of a first type of conductivity, wherein each semiconductor recess houses a plurality of memory words including a plurality of memory cells, wherein each memory cell includes a state transistor having a floating gate and a control gate. The memory device further includes a plurality of control gate selection transistors respectively allocated to each memory word of the plurality of memory words, wherein each control gateselection transistor is coupled to the control gates of the state transistors of the memory word to which the control gate selection transistor is allocated, wherein each control gate selection transistor is situated in and on a neighbor semiconductor recess of the semiconductor recess housing the memory word to which the control gate selection transistor is allocated.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from French Patent Application No. 1757908 filed on August 28, 2017, which is hereby incorporated by reference. technical field [0003] Embodiments relate to memory, particularly non-volatile memory, and in certain embodiments to non-volatile memory having constrained (eg, compact) size. Background technique [0004] Typically in an EEPROM memory device, a memory cell comprises a state transistor intended to store an item of information. The state transistor includes a control gate and a floating gate in series with an access transistor or a bit line select transistor. The access transistor is controlled by the word line signal and makes it possible to electrically access the state transistor, in particular in order to read a data item from it or write a data item to it. [0005] The control gate select transistor is connected between the gate control line and the control gate of th...

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Problems solved by technology

[0018] However, it is desirable to limit the use of the surface area of ​​the semiconductor substrate supporting the integrated circuit, so a split voltage solution may not be suitable, for example for applications including already small Low-density memory of the memory plane, which therefore cannot accept large surface areas at the periphery

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