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Clock network architecture for testability design

A network structure and clock technology, applied in computing, special data processing applications, instruments, etc., can solve problems such as unsatisfactory requirements, and achieve the effects of improving design efficiency, facilitating clock management and configuration, and clear clock architecture

Pending Publication Date: 2019-03-12
中科曙光信息产业成都有限公司 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The above structure has limitations and cannot meet the requirements

Method used

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  • Clock network architecture for testability design
  • Clock network architecture for testability design
  • Clock network architecture for testability design

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Embodiment Construction

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0034] An embodiment of the present invention provides a clock network structure for testability design. The clock network structure includes a top-level control unit and a module control unit. The top-level control unit is composed of a clock control unit corresponding to a PLL clock and a PLL frequency-divided clock The module control unit ...

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Abstract

The present invention provides a clock network architecture for a testability design. The clock network structure of the testability design comprises a top-level control unit and a module control unit. The top-level control unit is composed of a PLL clock and a clock control unit corresponding to a PLL frequency division clock. The module control unit is composed of a clock control unit inside a test module. The top-level control unit is used for providing a clock source of the module control unit and a clock connected to the test module, and the module control unit is used for providing a clock for testing the internal logic structure of the test module. The invention can carry out hierarchical network design in the early stage according to the test target, flexibly control different testmodes, and is convenient for designers to manage and configure clocks.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a clock network structure for testability design. Background technique [0002] With the rapid development of semiconductor integrated circuits, the scale of digital chips continues to increase, and design for test (Design for Test) is increasingly valued by chip designers. [0003] In design for testability, the path of the test clock is different from that of the normal working clock. When designing for testability, it is necessary to add additional logic to control the clock so that it can generate the desired waveform during the test. For example, for the scan test (san_test), the slow clock (shift_clk) from an external pin needs to be used in the shift phase (shift), and different clocks should be used in the capture phase (capture) according to different test modes. For the stuck-at-fault scan test (stuck_at_test), a slow clock is required for the capture...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/392
Inventor 张志强赵军张心标曾辉
Owner 中科曙光信息产业成都有限公司