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A Duty Ratio Multiplication Circuit of Pulse Width Modulation Signal Based on Clock Period

A pulse width modulation signal and clock signal technology, applied in the direction of pulse duration/width modulation, pulse technology, pulse generation, etc., can solve the problem of unable to adjust the signal, and achieve the effect of convenient duty cycle multiplication function

Active Publication Date: 2020-08-04
LINEARIN TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Many traditional pulse width modulation (PWM) signals are generated by analog circuits. Once generated, they cannot be effectively signal-conditioned, resulting in greater limitations in applications.
[0003] In the practice of the circuit system, it is necessary to perform duty cycle multiplication processing on the existing PWM signal, so as to realize the function of accurately doubling the analog quantity and facilitate the precise control of the system, but the traditional method cannot realize this function.

Method used

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  • A Duty Ratio Multiplication Circuit of Pulse Width Modulation Signal Based on Clock Period
  • A Duty Ratio Multiplication Circuit of Pulse Width Modulation Signal Based on Clock Period
  • A Duty Ratio Multiplication Circuit of Pulse Width Modulation Signal Based on Clock Period

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Embodiment 1

[0059] like image 3 As shown, in one embodiment of the present invention, for the purpose of multiplying the duty ratio of the high-level pulse of the pulse width modulation signal, the multiplication factor is 2 times, the period of the clock signal CLK is T, and the original pulse width modulation signal PWM1 The rising edge and falling edge of the signal PWM1 (hereinafter referred to as the signal PWM1) are synchronized with the rising edge of the clock signal CLK, and the high-level pulse width of the signal PWM1 is 2T, and the low-level pulse width of the signal PWM1 is 6T, that is, the signal PWM1 The duty cycle of the high-level pulse is 2T / (2T+6T)=1 / 4.

[0060] The rising edge of the signal PWM1 triggers the duty ratio multiplication start enable pulse generating circuit 201 to output the PWM multiplication start enable pulse Pulse1, the pulse width of which is T.

[0061] The first count value Count1 output by the first counter 203 is reset to 0 at the rising edge o...

Embodiment 2

[0065] like Figure 4 As shown, in another embodiment of the present invention, for the purpose of multiplying the duty cycle of the low-level pulse of the pulse width modulation signal, the multiplication factor is 2 times, the period of the clock signal CLK is T, and the original pulse width modulation signal The rising edge and falling edge of PWM1 (hereinafter referred to as signal PWM1) are synchronized with the rising edge of clock signal CLK, and the low-level pulse width of signal PWM1 is 2T, and the high-level pulse width of signal PWM1 is 6T, that is, signal PWM1 The duty cycle of the low-level pulse is 2T / (2T+6T)=1 / 4.

[0066] The falling edge of the signal PWM1 triggers the duty ratio multiplication start enable pulse generating circuit 201 to output the PWM multiplication start enable pulse Pulse1, the pulse width of which is T.

[0067] The first count value Count1 output by the first counter 203 is reset to 0 at the falling edge of the signal PWM1, and then it ...

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Abstract

A clock cycle-based pulse width modulation signal duty cycle multiplication circuit, comprising: a duty cycle multiplication enabling pulse generating circuit (101), an input end thereof inputting a clock signal (CLK) and an original pulse width modulation signal (PWM1), the duration of a high level and low level of the original pulse width modulation signal (PWM1) being the sum of an integer number of clock cycles of the clock signal (CLK), while an output end outputs a PWM multiplication start enabling pulse signal (Pulse1) and a PWM multiplication end enabling pulse signal (Pulse2); and a duty cycle multiplication circuit (102), an input end thereof inputting the PWM multiplication start enabling pulse signal (Pulse1) and the PWM multiplication end enabling pulse signal (Pulse2), and an output end outputting a PWM multiplication pulse width modulation signal (PWM2); the pulse width of the pulse width modulation signal after duty cycle multiplication (PWM2) is adapted to the PWM multiplication start enabling pulse signal (Pulse1) and the PWM multiplication end enabling pulse signal (Pulse2), and the pulse width modulation signal after duty cycle multiplication (PWM2) performs signal synchronization by means of the clock signal (CLK) to ensure that the duration of both a high level and low level of the pulse width modulation signal after duty cycle multiplication (PWM2) is the sum of an integer number of clock cycles of the clock signal (CLK). By means of synchronizing the original pulse width modulation signal (PWM1) and on the basis of a clock cycle, by cooperating with a corresponding control circuit, it is very convenient to achieve a duty cycle multiplication function for PWM signals.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a clock cycle-based pulse width modulation signal duty ratio multiplication circuit in the field of signal processing. Background technique [0002] Pulse Width Modulation (PWM) signal is a very common type of signal in electronic systems. It has dual attributes of analog signal and digital signal, and plays an important role in signal acquisition and transmission, signal conditioning, sensors, signal isolation and other fields. Many traditional pulse width modulation (PWM) signals are generated by analog circuits, and once generated, they cannot be effectively signal-conditioned, resulting in relatively large limitations in applications. [0003] In the practice of the circuit system, it is necessary to perform duty cycle multiplication processing on the existing PWM signal, so as to realize the function of accurately doubling the analog quantity and facilitate the precise con...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/017H03K5/05H03K7/08
CPCH03K3/017H03K5/05H03K7/08
Inventor 朱金桥
Owner LINEARIN TECH CORP