A Duty Ratio Multiplication Circuit of Pulse Width Modulation Signal Based on Clock Period
A pulse width modulation signal and clock signal technology, applied in the direction of pulse duration/width modulation, pulse technology, pulse generation, etc., can solve the problem of unable to adjust the signal, and achieve the effect of convenient duty cycle multiplication function
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Embodiment 1
[0059] like image 3 As shown, in one embodiment of the present invention, for the purpose of multiplying the duty ratio of the high-level pulse of the pulse width modulation signal, the multiplication factor is 2 times, the period of the clock signal CLK is T, and the original pulse width modulation signal PWM1 The rising edge and falling edge of the signal PWM1 (hereinafter referred to as the signal PWM1) are synchronized with the rising edge of the clock signal CLK, and the high-level pulse width of the signal PWM1 is 2T, and the low-level pulse width of the signal PWM1 is 6T, that is, the signal PWM1 The duty cycle of the high-level pulse is 2T / (2T+6T)=1 / 4.
[0060] The rising edge of the signal PWM1 triggers the duty ratio multiplication start enable pulse generating circuit 201 to output the PWM multiplication start enable pulse Pulse1, the pulse width of which is T.
[0061] The first count value Count1 output by the first counter 203 is reset to 0 at the rising edge o...
Embodiment 2
[0065] like Figure 4 As shown, in another embodiment of the present invention, for the purpose of multiplying the duty cycle of the low-level pulse of the pulse width modulation signal, the multiplication factor is 2 times, the period of the clock signal CLK is T, and the original pulse width modulation signal The rising edge and falling edge of PWM1 (hereinafter referred to as signal PWM1) are synchronized with the rising edge of clock signal CLK, and the low-level pulse width of signal PWM1 is 2T, and the high-level pulse width of signal PWM1 is 6T, that is, signal PWM1 The duty cycle of the low-level pulse is 2T / (2T+6T)=1 / 4.
[0066] The falling edge of the signal PWM1 triggers the duty ratio multiplication start enable pulse generating circuit 201 to output the PWM multiplication start enable pulse Pulse1, the pulse width of which is T.
[0067] The first count value Count1 output by the first counter 203 is reset to 0 at the falling edge of the signal PWM1, and then it ...
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