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SMV model construction method for register transfer level verilog code

A technology of register transfer level and construction method, which is applied in the field of SMV model construction of register transfer level Verilog code, can solve problems such as poor independence, and achieve good practical effect

Active Publication Date: 2021-01-05
NORTHWESTERN POLYTECHNICAL UNIV +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In order to overcome the deficiencies in the poor independence of the SMV model building method of the existing register transfer level, the present invention provides a SMV model building method of the register transfer level Verilog code

Method used

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  • SMV model construction method for register transfer level verilog code
  • SMV model construction method for register transfer level verilog code
  • SMV model construction method for register transfer level verilog code

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Embodiment Construction

[0020] refer to Figure 1-4 . The concrete steps of the SMV model construction method of the register transmission level Verilog code of the present invention are as follows:

[0021] Select RS232-T600 on Trust-Hub as the analysis object, which contains three Verilog files: uart.v, u_xmit.v and u_rec.v. The three Verilog files are shown below. There are hardware Trojans in the file u_xmit.v. The hardware Trojan is a finite state machine, which detects the sending data sequence, when the sequence 8'hAA, 8'h55, 8'h00 and 8'hFF appears, the Trojan is activated, the output variable xmit_doneH is set to "1", and The 7th bit of the transmitted data is replaced.

[0022] 1.uart.v program source code:

[0023]

[0024]

[0025] 2.u_xmit.v program source code:

[0026]

[0027]

[0028]

[0029]

[0030] 3.u_rec.v program source code:

[0031]

[0032]

[0033]

[0034] Step 1, generation of variable list.

[0035] Take lines 60-67 of u_xmit.v as an ...

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Abstract

The invention discloses an SMV model construction method of register transmission level Verilog codes. The method is used for solving the technical problem that an existing SMV model construction method of the register transmission level is poor in independence. According to the technical scheme, a method for statically analyzing Verilog codes is adopted to obtain a control flow graph corresponding to each module, the control flow graph is deeply traversed to obtain a (pc, exp) list of each variable in the module, and an SMV model corresponding to the module is constructed by utilizing the (pc, exp) list, Wherein pc is a path condition, and exp is an expression of a variable when pc is true. According to the method, after the Verilog code is read, for the generated analysis tree of the Verilog code, conversion and storage of the data format do not need to be carried out by relying on a third-party tool, the method can be used as an independent method to directly convert the input Verilog code into an SMV model, and the practicability is good.

Description

technical field [0001] The invention relates to a register transfer level SMV model building method, in particular to a register transfer level SMV model building method for Verilog codes. Background technique [0002] Most of the existing model checking models are based on gate-level circuits, and the established models are much more complicated than those at the register transfer level, which is not conducive to the designer's analysis and verification results. In the currently published technology and literature, the model checking verification method for hardware design security at the register transfer level is very limited. [0003] The document "Verilog2SMV: A tool for word-level verification, 2016Design, Automation&Test in Europe Conference&Exhibition (DATE), Dresden, 2016, pp.1156-1159" discloses a register transfer level Symbolic Model Verifier (hereinafter referred to as SMV) model construction Method for verifying register-transfer-level Verilog code. In this m...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F8/35
Inventor 沈利香慕德俊曹国徐强时翔袁晓宇潘群
Owner NORTHWESTERN POLYTECHNICAL UNIV
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