67 results about "Verilog code" patented technology

The invention discloses a coding and decoding method and device of elliptical curve, which comprises the following steps: a. obtaining or generating coding and decoding parameter E, G, n, H (), F (), Enc (), Dec (); selecting elliptical curve E and G as one point on the curve with limit area.

The invention discloses a Gaussian error function circuit applied to neural networks. The Gaussian error function circuit comprises three squarers, two multipliers, two multiplier-adders, two dot product digital signal processors, an adder, a derivation DSP, and an exponent DSP. The DSPs are Design Ware floating-point DSPs from Synopsys. The circuit has a simple structure, uses DSPs easy to obtain, and is easy to implement. Compared with the traditional Taylor expansion method implementation scheme, the circuit has very obvious advantages in terms of precision, area and speed, and especially, the precision is at least two orders of magnitude higher. Meanwhile, the circuit can be implemented using a Verilog code, and has nothing to do with any specific process, so that the circuit can be applied to different processes very easily and is of very strong portability. The Gaussian error function circuit can be applied to the design of various hardware circuits related to neural networks as a soft-core IP.

The invention relates to an automatic Verilog HDL code generator of a parallel CRC (Cyclic Redundancy Check) algorithm and a method thereof. The generator comprises a coefficient generation circuit based on a modelsim simulation platform, a coefficient file C.txt generated by operating a coefficient generation circuit code CG.v and a Verilog code file F.txt generated by operating a Verilog code generation file VG.v. The method comprises the following steps of: (1) extracting design parameters of N, M, A and INT; (2) obtaining the coefficient generation circuit by the design parameters of N, M, A and INT according to the design steps of the coefficient generation circuit; (3) expressing the coefficient generation circuit as CG.v by using the Verilog code; (4) obtaining the coefficient file C.txt by operating the CG.v; and (5) obtaining a Verilog code F.txt of the parallel CRC circuit by operating VG.v. In the invention, the Verilog HDL code generation of the parallel CRC algorithm is simplified.

The invention relates to an EDA (electronic design automation) and FPGA (field programmable gate array) reusable verification system for passive tag chips. The EDA and FPGA reusable verification system comprises an EDA environment verification system and an FPGA environment verification system. A reader verilog model (2) and a DUT (device under test) (7) in the EDA environment verification system and a reader verilog model (1-3) and a DUT (1-10) in the FPGA environment verification system can be reused mutually. The EDA and FPGA reusable verification system has the advantages that the readers and verilog codes of tags can be reused in EDA and FPGA verification environments in the verification systems, accordingly, codes for EDA and FPGA are identical, RTL (resistor transistor logic) codes do not need to be modified between the two verification systems, and high risks due to little modification can be prevented.

The invention relates to the technical field of computers, and discloses a debugging interface management method and device and electronic equipment. The method comprises the following steps: receiving an instruction input by a user for opening an Android debugging bridge (ADB) interface of equipment; acquiring a communication number bound with a debugging interface management function of the equipment according to the instruction; sending a first verification code to the acquired communication number; receiving a second verification code input by the user; and if the second verification codeis matched with the first verification code, opening the ADB interface. By means of the mode, the safety of ADB interface connection is improved.

The invention provides a verification code processing method and device, a terminal and a storage medium, and relates to the technical field of data processing. The method comprises the steps of obtaining a verification code image from a verification page, wherein the verification code image is an image of an area where a verification code is located in the verification page; sending the coding task to a server, so that the server sends the coding task to the target coding terminal; receiving code printing operation information, sent by the target code printing terminal through the server, fora page corresponding to the code printing task; and verifying the verification code in the verification page according to the coding operation information. The verification terminal sends a coding task to the target coding terminal through the server; the target coding terminal determines the coding operation information according to the operation of the coding personnel, the verification terminal verifies the verification code according to the coding operation information, more professional testers are not needed, the cost is saved, the coding personnel do not need to have professional testskills, and the verification code test efficiency is also improved.

The invention is suitable for the technical field of computer application, and provides a verification code generation method and device, and the method comprises the steps: generating a character sequence, wherein the character sequence is composed of letters and numbers; extracting code types corresponding to characters in the character sequence from a preset code type library; and deforming andcombining the code types to obtain the verification code. Through determining code type corresponding to a character sequence, deforming and combining the code types to obtain a verification code; and finally, generating a character matrix consisting of characters. In the character matrix, the characters with contrast form the image which can be recognized by human eyes and is composed of the characters, the requirement that the characters can be recognized by human beings but are difficult to recognize by machines is met through the display mode of the image, the use requirement of the character terminal is met, and the safety of verification code verification in the character terminal is also improved.

The invention discloses a standard answer generation method of an on-line Verilog code automatic judgment system. According to the title, correct Verilog code is compiled, a. Vwf waveform file is edited and simulated to generate. Do and. Vt files; . Do file and. Vt file are analyzed and modified to generate new. Do file and. Vt file; a standard answer.cmp file is generated to load into the answerlibrary; each file in the invention constructs the operation of the whole Verilog answer decision system, and ensures that the decision system can give a correct result.

The invention discloses an automatic scoring method of an on-line Verilog code automatic judgment system. The system accesses a standard answer database and copies the corresponding standard answer file and stores it in a temporary folder. The system runs the. Do file in the standard answer folder, and the. Vt file compiles the Verilog code file submitted by the students, and loads the library. The system runs modelsim in Linux to simulate. Vt, performs simulatin according to Verilog file submitted by students, and intercepts the console to output to. Result file; according to the time range written in the. Tm file, the system compares the simulation results. Result file with the standard answer. Cmp file to get the score result The. Do file of the invention compiles the student answer. Vfile and the. Vt file in the answer folder by using the vsim instruction, and simulates according to the. Vt file. The modules to be tested, the excitation of each signal, and the instructions to grabthe signal are written in the. Vt file. Thus, the whole Verilog code decision system is constructed, and the cost of Verilog class decision is greatly reduced.

The invention provides a dual verification method for trusted equipment to access an application, which comprises the following steps that: when an existing account accesses a new unauthorized client mode, a verification server verifies a current client A by adopting the following modes: the verification server randomly generates a dynamic code plaintext, encrypts the dynamic code plaintext, a dynamic code ciphertext is obtained, and then the dynamic code ciphertext is sent to the authorized client; the authorization client carries out decryption operation on the received dynamic code ciphertext to obtain a dynamic code plaintext, and the dynamic code plaintext is displayed in a display area of the authorization client; and the verification server judges whether the dynamic code plaintext returned by the client A is received within a preset time. The double-verification method for the trusted equipment to access the application has the advantages that a double-verification mechanism of the password and the verification code of the user account is adopted, and the safety of the user account in using the application software is remarkably enhanced.

The invention discloses a memory, a verification code implementation method, a verification code implementation device and verification code implementation equipment. The verification code implementation method comprises the following steps: acquiring a verification picture comprising a preset graph; prompting a user to draw in the verification picture according to the track of the preset graph; generating a drawing result according to the drawing behavior of the user; judging whether the drawing result is matched with the track of the preset graph or not; and generating a verification resultaccording to the judgment result. According to the method and the device, the difficulty of obtaining the graph consistent with the preset graph by a malicious computer program in a traversal mode isgreat, the operand is very large, and the required time length is very long, so that the method and the device are difficult to realize in a verification process. Therefore, through the embodiment ofthe invention, the probability that the malicious computer program passes the verification can be effectively reduced, and the safety of identity verification is further improved.

Redundancy information is added to information to be sent over a medium and sent as spatially coupled chain with the redundancy information as local decision verification codes. In the receiving end, when the local decision verification code has been satisfied a preset number of times, a sliding window is shifted.

The invention discloses a Verilog coding method achieving ATE test waveform by the adoption of FPGA. Description of a vector period signal set is constructed through task statements, an ATE test period vector is analyzed, and a periodic type set is classified; specific description is conducted on signal behaviors corresponding to all types of periods in the period type set in a vector period signal description set area of Verilog codes, a vector period signal description set is constructed, and period signal waveform is adopted for all period signals in the vector period signal description set to serve as characteristic keywords to be used as an identification naming period description name; Case conditional statements are applied, the number of vector periods serves as the triggering condition of the Case statements, the cycle description name serves as a condition selection object, and the period description name is in linkage with a designated clock period number, so that a vector output list corresponding to ATE test vector description is constructed. By means of the Verilog coding method achieving ATE test waveform by the adoption of the FPGA, efficiency and flexibility of development of converting from the ATE test vector to an FPGA design, development difficulty can be reduced, and design efficiency can be improved.

The invention discloses an information processing method and device for reducing the error rate of a digital circuit, and the method comprises the steps: obtaining a pulse signal set which comprises first, second pulse information to the Nth pulse information, and obtaining the corresponding reserved verification code information according to all pulse information; copying and storing all the reserved verification code information on M pieces of equipment respectively, and obtaining first access verification code information according to the first pulse information; verifying the first accessverification code information through the first reserved verification code to obtain a verification result; and according to the verification result, determining whether the first access permission isobtained, and accessing the first pulse information to the output end. The technical problems that in the prior art, a filter is used for filtering processing, but interference factors are diversified, the filtering effect is limited, the reliability of signal transmission cannot still be guaranteed, and errors exist are solved. The technical effects of encrypting the signal in the digital circuit by using the blockchain technology, ensuring the stability of the signal transmission process and reducing the circuit error rate are achieved.

The invention discloses a verification code generation method and device, and relates to the technical field of computers. A specific embodiment of the method comprises: obtaining a target character set used for generating a verification code; for each character in the target character set, generating a sub-adversarial sample; and combining the sub-adversarial samples corresponding to the characters in the target character set to generate a verification code. According to the embodiment, the security problem existing in the prior art due to the adoption of universal adversarial samples is solved, so that the technical effects of not influencing the readability of the user and improving the security of the verification code can be achieved.

The low-power-consumption time-based dynamic two-dimensional code device comprises a machine body and an upper cover. Buckling columns are symmetrically and optically connected to the two sides of themachine body, a display screen is arranged in the middle of an inner cavity of the upper cover, buckling grooves are symmetrically and fixedly formed in the two sides of the inner cavity of the uppercover, and pressure buttons are arranged in the buckling grooves. The invention relates to the technical field of two-dimensional codes. The dynamic two-dimensional code can be generated, the two-dimensional code comprises the time information, the product information and the verification code, the dynamic two-dimensional code information is displayed on the display screen, and when the dynamic two-dimensional code is collected, the dynamic two-dimensional code can accurately provide the real-time information of the product. And great convenience is brought to people to trace and verify product information. The machine body and the upper cover are better fastened together by clamping the buckle column covers in the buckle grooves in the two sides of the inner side of the upper cover, andthe buckle columns are bounced off from the buckle grooves by the pressure buttons on the two sides of the upper cover, so that maintenance and disassembly in the future are facilitated.