23 results about "Verilog code" patented technology

The invention discloses an integrated circuit design Verilog code generation method and device based on a large language model, equipment and a medium, and relates to the technical field of computers, and the method comprises the steps that semantic analysis is conducted on an input language of an integrated circuit user side through the large language model, and a target constraint set is determined based on an obtained performance index set and through a regular expression; a candidate architecture scheme is generated by utilizing thinking chain technology reasoning, the candidate architecture scheme is predicted by utilizing an XGBoost regression model, and a target architecture scheme is determined based on an index prediction result and the candidate architecture scheme by utilizing a non-dominated sorting genetic algorithm; and determining an initial Verilog code based on the target architecture scheme and a preset code template library, and performing code style conversion on the initial Verilog code based on a code style feature corresponding to the integrated circuit user side to obtain a target Verilog code. And the efficiency and availability of integrated circuit design are improved.

The invention provides a verification code verification method and device, equipment, a medium and a program product, and aims to solve the problem that an automatic script in the related technology cannot realize automatic testing of verification of a verification code of a rotary sliding block. The method comprises the steps of performing separation processing on a rotating main body and a target pattern in a verification code image to obtain a main body binary mask corresponding to the rotating main body and a target binary mask corresponding to the target pattern; based on the main body binary mask and the target binary mask, a target angle difference between the rotating main body and the target pattern is calculated, and the target angle difference is used for indicating the rotating main body to rotate to a rotating angle matched with the target pattern; generating a rotation track based on the target angle difference by using a slow motion function, wherein the rotation track comprises random disturbance and a random pause point; and controlling the rotating main body to rotate based on the rotating track to obtain a verification result. According to the invention, automatic testing of verification of the rotary sliding block verification code can be realized.

A system and method for zero-knowledge verifiable codebook compression receives an input data stream comprising data blocks and encodes the stream using codebook-based compression algorithms. Concurrently with encoding, the system generates zero-knowledge proofs that cryptographically attest that the encoded representation will decode to data having a specified digest and that policy appendices associated with the codebook were applied during encoding. The system generates codebook commitments comprising cryptographic commitments to codebook contents and policy metadata, then formats output packets containing the encoded representation, zero-knowledge proof, and public inputs including the specified digest and codebook commitment. The zero-knowledge proofs enable verification systems to validate encoding correctness and policy compliance without accessing plaintext content or codebook contents.

Systems, apparatuses, methods, and computer program products are disclosed for secure utilization of quick response (QR) codes. An example method includes obtaining a key known to an initiating device and a participating device, and receiving, by the communications hardware of the participating device, an indication of a secure character string extracted from a QR code. The example method further includes verifying, by security circuitry of the participating device and using the key, authenticity of the QR code, and performing by the participating device, an action set.

A method for operating a secure programming system is provided. Firstly, a first verification code is calculated according to a payload extracted from a job control package. Then, a second verification code is calculated according to the payload burnt into a programmable device. If the first verification code and the second verification code are verified successfully, a burning task is performed. Then, an OEM certificate signing request is generated according to an identifiable information and a programmable device public key. If the OEM certificate signing request is verified successfully, an OEM device certificate is generated and signed with an OEM private key. A third verification code is calculated according to the OEM device certificate. Then, a fourth verification code is calculated according to the OEM device certificate burnt into the programmable device.

The invention provides a Verilog code repair method and system based on compiler feedback drive and Agent, and the method comprises the steps: obtaining a defect code, and carrying out the preprocessing, and obtaining a preprocessed defect code; constructing a structured abstract syntax tree AST; a Verilog compiler is used for compiling the preprocessed codes, error information is collected, error positions are mapped to corresponding nodes in a structured AST, and line-level and grammar node-level positioning is achieved; performing an iterative repair cycle based on the Agent to obtain a repaired Verilog source code; and outputting the restored Verilog source code and the restoration report. According to the Verilog code repairing method and system based on the compiler feedback driver and the Agent, the hierarchical structure and semantics of the Verilog code can be deeply understood, and the repairing accuracy and reliability can be remarkably improved.

1. Name of the product in this design: Graphical User Interface for a Children's Digital Community Platform for Electronic Devices. 2. Application of this design: This design is intended for use in an electronic device. 3. The key design features of this product are its graphical user interface. 4. The image or photo that best illustrates the design points: Design 1 Interface Changes Unfolding Diagram 1. 5. Design 3 is designated as the basic design. 6. Purpose of the graphical user interface: The graphical user interface of the product is the software interface of the children's digital community platform; the main view of Design 1 is the software login interface; the expanded diagram of the interface of Design 1 is the interface displayed after correctly entering the username, password and verification code on the main view of Design 1 and clicking the "Login" button; the expanded diagram of the interface of Design 1 is the interface displayed after clicking the "Community Garden" option in the left menu bar of the expanded diagram of the interface of Design 1. Design 2 is a similar design. The main view of Design 2 is the software login interface. The expanded view of the interface changes in Design 2 is the interface displayed after correctly entering the username, password, and verification code on the main view of Design 2 and clicking the "Login" button. The state diagram of the interface changes in Design 2 is the interface displayed after clicking the "Parents' Board" option in the left menu bar of the expanded view of the interface changes in Design 2. Design 3 is a similar design. The main view of Design 3 is the software login interface. The expanded interface diagram 1 of Design 3 is the interface displayed after correctly entering the username, password, and verification code on the main view of Design 3 and clicking the "Login" button. The expanded interface diagram 2 of Design 3 is the interface displayed after clicking the "Cultural Kaleidoscope" option in the interface of the expanded interface diagram 1 of Design 3. The expanded interface diagram 3 of Design 3 is the interface displayed after swiping up on the interface of the expanded interface diagram 2 of Design 3. Design 4 is a similar design. The main view of Design 4 is the software login interface. The expanded interface diagram 1 of Design 4 is the interface displayed after correctly entering the username, password, and verification code on the main view of Design 4 and clicking the "Login" button. The expanded interface diagram 2 of Design 4 is the interface displayed after clicking the "Future Inventor" option in the expanded interface diagram 1 of Design 4. The expanded interface diagram 3 of Design 4 is the interface displayed after swiping up on the expanded interface diagram 2 of Design 4. Design 5 is a similar design. The main view of Design 5 is the software login interface. The expanded interface diagram 1 of Design 5 is the interface displayed after correctly entering the username, password, and verification code on the main view of Design 5 and clicking the "Login" button. The expanded interface diagram 2 of Design 5 is the interface displayed after clicking the "Digital Canvas" option in the expanded interface diagram 1 of Design 5. Design 6 is a similar design, the design 6 main view is a software login interface, the design 6 interface change expansion view is an interface displayed after clicking the "login" button after correctly inputting the username, password, and verification code on the design 6 main view; the design 6 interface change state view is an interface displayed after clicking the "story weaving machine" option in the design 6 interface change expansion view interface. Design 7 is a similar design, the design 7 main view is a software login interface, the design 7 interface change expansion view 1 is an interface displayed after clicking the "login" button after correctly inputting the username, password, and verification code on the design 7 main view; the design 7 interface change expansion view 2 is an interface displayed after clicking the "music laboratory" option in the design 7 interface change expansion view 1 interface. Among them, limited by the screen size, the interface change state view cannot be fully displayed, so the interface change expansion view is used for display.

The invention provides an automatic Verilog code generation method and system based on AST grammar semantic enhancement, and the method comprises the steps: obtaining a Verilog source code, and obtaining a preprocessed source code; compiling and simulation dual verification and pre-screening are carried out; generating an abstract syntax tree AST, and extracting key structure information; static analysis driven semantic enhancement is performed based on a tree structure of an AST, and semantic information is deduced and labeled for nodes by traversing the nodes of the AST and according to a heuristic rule, so that a semantic enhanced AST is generated; constructing a training data set for generating the Verilog code by using the Verilog source code, a semantic enhanced abstract syntax tree AST and a structured semantic prompt; a fine-tuned model is obtained; and generating a Verilog code. Experimental verification shows that the method is obviously superior to a traditional model in the aspects of compilation success rate and structural consistency.

1. Name of the product in this design: Electronic device for business opportunity management user interface. 2. Purpose of this design: For running programs and displaying interfaces. 3. The key design feature of this product is its graphical user interface. 4. The image or photograph that best illustrates the design's key points: the front view. 5. As is customary, rear view, left view, right view, top view, and bottom view are omitted. 6. Description of the changing states of the graphical user interface: The main view is the main interface of the user interface. After entering the username, password and verification code, click "Login". The interface will jump to the interface changing state diagram 1. Click the "Business Opportunities" button in the interface changing state diagram 1. The interface will jump to the interface changing state diagram 2. Click the "Main Equipment and Materials" button in the interface changing state diagram 2. The interface will jump to the interface changing state diagram 3. Click the "Add Equipment and Material Template" button in the interface changing state diagram 3. The interface will jump to the interface changing state diagram 4. Select "Bulk Carrier" in the interface changing state diagram 4. The interface will jump to the interface changing state diagram 5. Click the "Add Materials" button in the interface changing state diagram 5. The interface will jump to the interface changing state diagram 6.

The application discloses a lightweight Verilog code generation method based on dual learning, comprising the following steps: adopting a Verilog code corpus to perform domain self-adapting pre-training on a pre-trained language model to obtain a domain-adapted language model; under a dual learning framework, fine-tuning the domain-adapted language model on a paired annotation data set to establish a mapping relationship from a natural language digital circuit hardware design description to a Verilog code, and obtaining a Verilog code generation model; receiving a natural language digital circuit hardware design description input by a user, generating multiple candidate Verilog codes by adopting a probability sampling strategy based on a temperature parameter; verifying the syntax compliance of the multiple candidate Verilog codes, and eliminating the candidate Verilog codes with syntax errors; calculating the confidence of the candidate Verilog codes with syntax compliance, sorting the candidate Verilog codes with syntax compliance according to the confidence, and outputting the Verilog code with the highest confidence as a generation result.

The invention provides a c code and verilog code generation method and device, and relates to the technical field of software development and FPGA board card debugging. When the method is executed, firstly, a model is built through GCKontrol modeling software, secondly, floating-point simulation is conducted on the model, thirdly, subsystem packaging is conducted on a module, needing to automatically generate the verilog code, in the model, then the module, needing to automatically generate the verilog code, in a subsystem is calibrated according to a floating-point simulation result, then, the calibrated model is simulated, and finally, the model is subjected to automatic generation of the verilog code. And finally, if the simulation result of the model accords with the expectation, generating a c code and a verilog code at the same time by utilizing the calibrated model. In this way, the c code and the verilog code are automatically generated at the same time.

This invention provides an automated Verilog code generation method and system based on AST (Abstract Syntax Tree) semantic enhancement. The method involves obtaining the Verilog source code, generating a preprocessed version, performing dual verification and pre-screening through compilation and simulation, generating an Abstract Syntax Tree (AST), and extracting key structural information. Semantic enhancement is then performed based on the tree structure of the AST, driven by static analysis. This involves traversing the AST nodes and inferring and labeling semantic information for each node according to heuristic rules, generating a semantically enhanced AST. A training dataset for Verilog code generation is constructed from the Verilog source code, the semantically enhanced AST, and structured semantic hints. A fine-tuned model is then obtained, and finally, Verilog code is generated. Experimental results show that this invention significantly outperforms traditional models in terms of compilation success rate and structural consistency.

A method for designing a time-domain non-stationary V2V MIMO communication channel emulator includes determining basic parameters for the V2V MIMO communication channel; generating a V2V 2D time-domain non-stationary communication channel environment, by using a MATLAB, that is, the numbers of the scatterers and the positions of the scatterers and the like; importing parameters generated in the previous step into a hardware simulation platform to calculate communication channel parameters for clusters, such as an angle distribution and a power distribution, writing a Verilog code for running, and eventually calculating to obtain a channel impulse response of the time-domain non-stationary V2V MIMO communication channel; and comparing with a statistical characteristic of a theoretical communication channel model, and designing an appropriate hardware diagram of a communication channel emulator. The method supports the simulation of time-domain non-stationary V2V MIMO communication channel, filling the gap in the field of communication channel emulators.

The application discloses an abnormal short message behavior detection method and system based on multi-dimensional feature fusion, relates to the related technical field of short message security detection, and comprises the following steps: collecting the space-time distribution features, semantic association graphs and device behavior fingerprints of short message interaction, configuring a dynamic feature pool, and extracting cross-modal feature sequences; performing cascade identification; dynamically adjusting a feature fusion weight matrix, generating an abnormal probability score, triggering a multi-stage verification mechanism when the abnormal probability score exceeds a dynamic abnormal probability threshold; matching the timing mode at an edge computing node, dynamically generating a verification code trigger threshold, and performing interactive risk verification to determine an abnormal short message behavior label. The application solves the technical problems of single detection dimension, difficulty in identifying new complex abnormal short message behaviors, and high false positive and false negative rates in the prior art, and achieves the technical effects of reducing the false positive and false negative rates of short message anomaly detection, improving the detection timeliness and adaptability.

An operating method for a secure programming system is provided. Firstly, the programmer encrypts a job control package including a payload. Then, a programmable device is loaded into the programmer. If an authentication code in an authentication list complies with a device identification code of the programmable device, the programmer decrypts the encrypted job control packages so as to extract the payload. Then, the programmer calculates a first verification code according to the payload, and the programmer burns the payload into the programmable device. Then, the programmer reads the burnt payload from the programmable device and calculates a second verification code according to the burnt payload. If the first verification code and the second verification code are verified successfully, the programmable device is categorized into a first output container representing a good output container.

This application discloses a code conversion method, apparatus, electronic device, and computer-readable storage medium, relating to the field of digital integrated circuit design automation technology. The method includes: parsing the SystemVerilog code to be converted to obtain an initial abstract syntax tree; parsing the type mapping relationships of the initial abstract syntax tree and establishing a global type mapping table based on the parsing results; performing semantic equivalence transformations on the syntax nodes in the initial abstract syntax tree based on the global type mapping table to obtain an intermediate abstract syntax tree; optimizing the intermediate abstract syntax tree to obtain a target abstract syntax tree; and generating Verilog code corresponding to the SystemVerilog code based on the target abstract syntax tree. This application can generate standardized, high-quality Verilog code while ensuring functional consistency, and can improve the accuracy, reliability, and overall efficiency of code conversion.

1. The name of the present design product: e-Infrastructure project reporting graphical user interface for electronic equipment. 2. The use of the present design product: for program running and data interaction. 3. The design points of the present design product: the graphical user interface content in the screen. 4. The picture or photo that best indicates the design points: front view. 5. Other views are omitted as they do not involve design points. 6. The use of the graphical user interface: the present design is used for the digital management and application of the e-Infrastructure 2.0 mobile terminal in the project reporting function. Click the switch button in the upper left corner of the front view, and the interface changes to the interface shown in interface change state diagram 1; select "XXXXXXXXXXXXX220kV substation project (single item)" in interface change state diagram 1, and the interface changes to the interface shown in interface change state diagram 2; click "Please select" below "Application start time" in interface change state diagram 2, and the interface changes to the interface shown in interface change state diagram 3; after completing the start time selection in interface change state diagram 3, click the "Confirm" button, and the interface changes to the interface shown in interface change state diagram 4; check "Examination item" in interface change state diagram 4, and the interface changes to the interface shown in interface change state diagram 5, click the "Sign and seal" button 5 in interface change state diagram 5, and the interface changes to the interface shown in interface change state diagram 6; click "Handwritten signature" in interface change state diagram 6, and the interface changes to the interface shown in interface change state diagram 7; after completing the signature in interface change state diagram 7, click the "Submit" button, and the interface changes to the interface shown in interface change state diagram 8; input "Login password" in interface change state diagram 8 and click "Next", and the interface changes to the interface shown in interface change state diagram 9; click "More" in the pop-up window below interface change state diagram 9, and the interface changes to the interface shown in interface change state diagram 10; select the target seal in interface change state diagram 10, and after completing the selection, the interface changes to the interface shown in interface change state diagram 11; click "√" in interface change state diagram 11, and the interface changes to the interface shown in interface change state diagram 12; click "Send SMS verification code" in interface change state diagram 12, and the interface changes to the interface shown in interface change state diagram 13; input the verification code in the box for inputting the verification code in interface change state diagram 13, and click Confirm, and the interface changes to the interface shown in interface change state diagram 14; click "Complete" in interface change state diagram 14, and the interface changes to the interface shown in interface change state diagram 15.

The invention provides a large language model-based floating point arithmetic unit Verilog code generation method, which comprises the following steps of: obtaining a total function document of a target FPU through LLM (Log Language Model) by using natural language function description of the target FPU; based on the total function document, performing function decomposition on a target FPU through LLM to obtain a plurality of function sub-modules and corresponding sub-function documents; updating the total function document by using all the sub-function documents; rewriting a Verilog sub-module code through LLM based on the sub-function document; based on the Verilog submodule code, obtaining an accuracy score of the total function document, and based on the total function document with the highest accuracy score, generating feedback information; functional decomposition and Verilog sub-module code rewriting are iteratively executed according to the feedback information, iteration operation is ended when an iteration termination condition is met, and a final Verilog code of the target FPU is generated according to the Verilog sub-module code when iteration is ended. The invention further provides a floating point arithmetic unit Verilog code generation device based on the large language model.

This invention relates to the field of computers and discloses a bus design generation method, apparatus, electronic device, and storage medium. The bus design generation method includes the following steps: determining boundary input interfaces and boundary output interfaces; wherein the boundary input interfaces are connected to the input-side module of the bus, and the boundary output interfaces are connected to the output-side module of the bus; generating a graphical description of the bus design based on the protocols supported by the boundary input interfaces and the boundary output interfaces; presenting the graphical description in a graphical interface; and, upon receiving a confirmation command, converting the graphical description into a Verilog code description of the bus. This bus design generation method enables rapid generation of bus designs.

The invention provides a method for training a Verilog code generator, and relates to the field of code generation. Wherein the sample set comprises a first Verilog code and a sample description thereof. And inputting the sample description into the initial Verilog code generator to obtain a second Verilog code. And inputting the second Verilog code into a discriminator corresponding to the first downstream task to obtain a discrimination result. And obtaining a discrimination loss value based on the discrimination result, and performing parameter adjustment on the initial Verilog code generator based on the code generation loss value and the discrimination loss value to obtain a target Verilog code generator. The judgment result is used for judging whether the second Verilog code meets the evaluation index specified by the user for the first downstream task or not, so that the judgment loss carries the information of the evaluation index, the code generation effect can be drawn by utilizing the judgment loss, the generated Verilog code is friendly to the first downstream task, and the chip design efficiency is improved.

The invention discloses a personalized short message verification code pushing method based on multi-task learning, and the method comprises the following steps: collecting original user data of a user, and carrying out the preprocessing; inputting to an improved AdaTT network, and carrying out multi-modal feature fusion and weight distribution; calculating a risk probability value after executing dynamic gating fusion with the task proprietary features, and comparing the risk probability value with a preset threshold value; performing cross-task correction and selecting an optimal channel after dynamic gating fusion is performed on the channel task features; after dynamic gating fusion processing is executed, cross-task interaction is carried out, probability distribution is output, and an optimal time window is selected; performing joint judgment, constructing a joint loss function and updating an initial short message verification code pushing strategy; and executing the pushing operation of the short message verification code based on the personalized short message verification code pushing strategy. According to the method, the improved AdaTT network is adopted, personalized short message verification code intelligent pushing is achieved, and the method has the advantages of being high in safety, flexible in strategy and excellent in user experience.

The invention discloses a multi-scene short message verification code pushing method based on a large language model. The method comprises the following steps of collecting context data and performing preprocessing; performing standardization processing and coding to generate a scene feature vector and a risk feature vector; constructing a model input sequence; reasoning by adopting an improved GTrXL large language model, and outputting a scene label and a risk level; calculating to obtain channel constraint data; performing strategy arrangement to generate a delivery plan; generating verification code short message content; and strategy parameters are updated, so that verification code short message pushing with high success rate, low delay and high security is realized, and the intelligent degree and the self-adaptive capability of the system are improved.

The invention relates to the technical field of privacy computing, in particular to a federal learning verifiable security aggregation method under double cloud servers, in a framework, each client performs three-group key negotiation with each auxiliary node to generate two groups of single-valued masks and a group of verification codes, and meanwhile, the masks are randomly generated. After the training is completed, the client horizontally splits the gradient, firstly performs respe operation on the gradient vector, and splits the two-dimensional vector after obtaining the two-dimensional vector; the sum of local key negotiation values is used as a mask for encryption, the sum of another group of key negotiation values and the gradient are used for generating a verification code, and the mask gradient and the verification code are respectively uploaded to two cloud servers for aggregation. And the double cloud servers aggregate gradients and verification codes respectively, mask elimination is carried out after total aggregation processing, then an aggregation model and an aggregation verification code are issued to the user, and the user verifies the correctness of the aggregation verification code. According to the invention, on the premise of ensuring relatively high security, the calculation overhead generated in the verification process is reduced.