49 results about "Verilog code" patented technology

The invention discloses an integrated circuit design Verilog code generation method and device based on a large language model, equipment and a medium, and relates to the technical field of computers, and the method comprises the steps that semantic analysis is conducted on an input language of an integrated circuit user side through the large language model, and a target constraint set is determined based on an obtained performance index set and through a regular expression; a candidate architecture scheme is generated by utilizing thinking chain technology reasoning, the candidate architecture scheme is predicted by utilizing an XGBoost regression model, and a target architecture scheme is determined based on an index prediction result and the candidate architecture scheme by utilizing a non-dominated sorting genetic algorithm; and determining an initial Verilog code based on the target architecture scheme and a preset code template library, and performing code style conversion on the initial Verilog code based on a code style feature corresponding to the integrated circuit user side to obtain a target Verilog code. And the efficiency and availability of integrated circuit design are improved.

The invention provides a verification code verification method and device, equipment, a medium and a program product, and aims to solve the problem that an automatic script in the related technology cannot realize automatic testing of verification of a verification code of a rotary sliding block. The method comprises the steps of performing separation processing on a rotating main body and a target pattern in a verification code image to obtain a main body binary mask corresponding to the rotating main body and a target binary mask corresponding to the target pattern; based on the main body binary mask and the target binary mask, a target angle difference between the rotating main body and the target pattern is calculated, and the target angle difference is used for indicating the rotating main body to rotate to a rotating angle matched with the target pattern; generating a rotation track based on the target angle difference by using a slow motion function, wherein the rotation track comprises random disturbance and a random pause point; and controlling the rotating main body to rotate based on the rotating track to obtain a verification result. According to the invention, automatic testing of verification of the rotary sliding block verification code can be realized.

A system and method for zero-knowledge verifiable codebook compression receives an input data stream comprising data blocks and encodes the stream using codebook-based compression algorithms. Concurrently with encoding, the system generates zero-knowledge proofs that cryptographically attest that the encoded representation will decode to data having a specified digest and that policy appendices associated with the codebook were applied during encoding. The system generates codebook commitments comprising cryptographic commitments to codebook contents and policy metadata, then formats output packets containing the encoded representation, zero-knowledge proof, and public inputs including the specified digest and codebook commitment. The zero-knowledge proofs enable verification systems to validate encoding correctness and policy compliance without accessing plaintext content or codebook contents.

Systems, apparatuses, methods, and computer program products are disclosed for secure utilization of quick response (QR) codes. An example method includes obtaining a key known to an initiating device and a participating device, and receiving, by the communications hardware of the participating device, an indication of a secure character string extracted from a QR code. The example method further includes verifying, by security circuitry of the participating device and using the key, authenticity of the QR code, and performing by the participating device, an action set.

The present invention provides an encoding method, a decoding method, and a node device for lightweight storage of a blockchain system. The encoding storage method uses a method in which, when storing an account book, a block is added to the account book and a code block generated by block encoding is stored; wherein, a Reed-Solomon encoder is used to encode the block fragment; then, a hash value of the codeword is calculated, a Merkle tree is constructed, and a Merkle proof is generated; finally, the codeword, the Merkle proof, and the block header of the block fragment corresponding to the codeword are packaged into a code block. In the decoding method, the node sends a decoding request to other nodes. When a code block is received from another node, the validity of the codeword of the code block is first verified, and then the codeword is placed in a codeword matrix. Finally, the inverse operation of the encoding is used to decode the codeword matrix to recover the block. The node device includes a memory used as a blockchain node repository, an encoder for executing the encoding storage method, and a decoder for executing the block decoding method.

A method for operating a secure programming system is provided. Firstly, a first verification code is calculated according to a payload extracted from a job control package. Then, a second verification code is calculated according to the payload burnt into a programmable device. If the first verification code and the second verification code are verified successfully, a burning task is performed. Then, an OEM certificate signing request is generated according to an identifiable information and a programmable device public key. If the OEM certificate signing request is verified successfully, an OEM device certificate is generated and signed with an OEM private key. A third verification code is calculated according to the OEM device certificate. Then, a fourth verification code is calculated according to the OEM device certificate burnt into the programmable device.

The invention provides a Verilog code repair method and system based on compiler feedback drive and Agent, and the method comprises the steps: obtaining a defect code, and carrying out the preprocessing, and obtaining a preprocessed defect code; constructing a structured abstract syntax tree AST; a Verilog compiler is used for compiling the preprocessed codes, error information is collected, error positions are mapped to corresponding nodes in a structured AST, and line-level and grammar node-level positioning is achieved; performing an iterative repair cycle based on the Agent to obtain a repaired Verilog source code; and outputting the restored Verilog source code and the restoration report. According to the Verilog code repairing method and system based on the compiler feedback driver and the Agent, the hierarchical structure and semantics of the Verilog code can be deeply understood, and the repairing accuracy and reliability can be remarkably improved.

1. Name of the product in this design: Graphical User Interface for a Children's Digital Community Platform for Electronic Devices. 2. Application of this design: This design is intended for use in an electronic device. 3. The key design features of this product are its graphical user interface. 4. The image or photo that best illustrates the design points: Design 1 Interface Changes Unfolding Diagram 1. 5. Design 3 is designated as the basic design. 6. Purpose of the graphical user interface: The graphical user interface of the product is the software interface of the children's digital community platform; the main view of Design 1 is the software login interface; the expanded diagram of the interface of Design 1 is the interface displayed after correctly entering the username, password and verification code on the main view of Design 1 and clicking the "Login" button; the expanded diagram of the interface of Design 1 is the interface displayed after clicking the "Community Garden" option in the left menu bar of the expanded diagram of the interface of Design 1. Design 2 is a similar design. The main view of Design 2 is the software login interface. The expanded view of the interface changes in Design 2 is the interface displayed after correctly entering the username, password, and verification code on the main view of Design 2 and clicking the "Login" button. The state diagram of the interface changes in Design 2 is the interface displayed after clicking the "Parents' Board" option in the left menu bar of the expanded view of the interface changes in Design 2. Design 3 is a similar design. The main view of Design 3 is the software login interface. The expanded interface diagram 1 of Design 3 is the interface displayed after correctly entering the username, password, and verification code on the main view of Design 3 and clicking the "Login" button. The expanded interface diagram 2 of Design 3 is the interface displayed after clicking the "Cultural Kaleidoscope" option in the interface of the expanded interface diagram 1 of Design 3. The expanded interface diagram 3 of Design 3 is the interface displayed after swiping up on the interface of the expanded interface diagram 2 of Design 3. Design 4 is a similar design. The main view of Design 4 is the software login interface. The expanded interface diagram 1 of Design 4 is the interface displayed after correctly entering the username, password, and verification code on the main view of Design 4 and clicking the "Login" button. The expanded interface diagram 2 of Design 4 is the interface displayed after clicking the "Future Inventor" option in the expanded interface diagram 1 of Design 4. The expanded interface diagram 3 of Design 4 is the interface displayed after swiping up on the expanded interface diagram 2 of Design 4. Design 5 is a similar design. The main view of Design 5 is the software login interface. The expanded interface diagram 1 of Design 5 is the interface displayed after correctly entering the username, password, and verification code on the main view of Design 5 and clicking the "Login" button. The expanded interface diagram 2 of Design 5 is the interface displayed after clicking the "Digital Canvas" option in the expanded interface diagram 1 of Design 5. Design 6 is a similar design, the design 6 main view is a software login interface, the design 6 interface change expansion view is an interface displayed after clicking the "login" button after correctly inputting the username, password, and verification code on the design 6 main view; the design 6 interface change state view is an interface displayed after clicking the "story weaving machine" option in the design 6 interface change expansion view interface. Design 7 is a similar design, the design 7 main view is a software login interface, the design 7 interface change expansion view 1 is an interface displayed after clicking the "login" button after correctly inputting the username, password, and verification code on the design 7 main view; the design 7 interface change expansion view 2 is an interface displayed after clicking the "music laboratory" option in the design 7 interface change expansion view 1 interface. Among them, limited by the screen size, the interface change state view cannot be fully displayed, so the interface change expansion view is used for display.

The invention provides an automatic Verilog code generation method and system based on AST grammar semantic enhancement, and the method comprises the steps: obtaining a Verilog source code, and obtaining a preprocessed source code; compiling and simulation dual verification and pre-screening are carried out; generating an abstract syntax tree AST, and extracting key structure information; static analysis driven semantic enhancement is performed based on a tree structure of an AST, and semantic information is deduced and labeled for nodes by traversing the nodes of the AST and according to a heuristic rule, so that a semantic enhanced AST is generated; constructing a training data set for generating the Verilog code by using the Verilog source code, a semantic enhanced abstract syntax tree AST and a structured semantic prompt; a fine-tuned model is obtained; and generating a Verilog code. Experimental verification shows that the method is obviously superior to a traditional model in the aspects of compilation success rate and structural consistency.

1. Name of the product in this design: Electronic device for business opportunity management user interface. 2. Purpose of this design: For running programs and displaying interfaces. 3. The key design feature of this product is its graphical user interface. 4. The image or photograph that best illustrates the design's key points: the front view. 5. As is customary, rear view, left view, right view, top view, and bottom view are omitted. 6. Description of the changing states of the graphical user interface: The main view is the main interface of the user interface. After entering the username, password and verification code, click "Login". The interface will jump to the interface changing state diagram 1. Click the "Business Opportunities" button in the interface changing state diagram 1. The interface will jump to the interface changing state diagram 2. Click the "Main Equipment and Materials" button in the interface changing state diagram 2. The interface will jump to the interface changing state diagram 3. Click the "Add Equipment and Material Template" button in the interface changing state diagram 3. The interface will jump to the interface changing state diagram 4. Select "Bulk Carrier" in the interface changing state diagram 4. The interface will jump to the interface changing state diagram 5. Click the "Add Materials" button in the interface changing state diagram 5. The interface will jump to the interface changing state diagram 6.

This invention proposes a flexible, optimized random number generation method based on FPGA lookup tables, belonging to the field of random number hardware generation technology. The method implements a Flexible Lookup Table (V-LUT) random number generator on a hardware FPGA, including: obtaining parameters of the V-LUT random number generator, which determine the generator's cycle length and resource usage; creating a state transition matrix using a V-LUT state transition matrix generation program; converting the state transition matrix into Verilog code to implement the corresponding FPGA circuit; configuring the FPGA circuit by optimizing the V-LUT random number generator parameters; and performing quality testing on the random numbers generated by the V-LUT random number generator. This invention allows the random number generator to better utilize the hardware characteristics of the FPGA, thereby improving the efficiency of random number generation.

The application discloses a lightweight Verilog code generation method based on dual learning, comprising the following steps: adopting a Verilog code corpus to perform domain self-adapting pre-training on a pre-trained language model to obtain a domain-adapted language model; under a dual learning framework, fine-tuning the domain-adapted language model on a paired annotation data set to establish a mapping relationship from a natural language digital circuit hardware design description to a Verilog code, and obtaining a Verilog code generation model; receiving a natural language digital circuit hardware design description input by a user, generating multiple candidate Verilog codes by adopting a probability sampling strategy based on a temperature parameter; verifying the syntax compliance of the multiple candidate Verilog codes, and eliminating the candidate Verilog codes with syntax errors; calculating the confidence of the candidate Verilog codes with syntax compliance, sorting the candidate Verilog codes with syntax compliance according to the confidence, and outputting the Verilog code with the highest confidence as a generation result.

This paper proposes a context-switching-oriented embedded CGRA secondary memory design method, including the following steps: Step 1: Determine the basic CGRA hardware architecture based on actual multitasking requirements; Step 2: Using the open-source CGRA modeling tool OpenCGRA, describe the CGRA hardware architecture using the PyMTL3 language based on the selected basic CGRA hardware architecture; Step 3: Modify the basic component library Mem provided by OpenCGRA and add components using the PyMTL3 language to complete the secondary design of the data memory in each tile, thereby obtaining the embedded CGRA; Step 4: Design the sequential logic for state transitions and state outputs, as well as the combinational logic for state switching, for all working states of the finite state machine in the secondary memory, and describe these using the PyMTL3 language; Step 5: Generate synthesizable Verilog code using OpenCGRA. This method can prevent task stalls during context switching, thereby improving task throughput.

The invention provides a CAN message filtering method for a distributed override trip prevention system. The CAN message filtering method comprises the following steps: determining a frame ID structure of a CAN message configured by the system; determining a positioning tag number configured by the system for the switch; and configuring a verification code and a shielding code of a receiving register according to the frame ID structure and a positioning tag number of a next-level switch, so that the receiving register filters a CAN message sent by a non-next-level switch. After the override trip prevention system message is filtered by adopting the method provided by the invention, a single switch only receives a useful override trip prevention system message and processes the message, and through hardware filtering, the consumption of processor resources is greatly reduced, the working efficiency of a processor is improved, the reliability and quick action of the override trip prevention system are improved, and the service life of the override trip prevention system is prolonged. Particularly, the more the node switches of the override trip prevention system are, the more obvious the performance improvement effect is.

The invention discloses a multi-port delivery coupon pushing method and device, and relates to the technical field of intelligent marketing, and the method comprises the steps: inputting a multi-modal feature tensor into an SNN decision engine, generating SNN synaptic weight parameters based on user historical behavior spatio-temporal features, and dynamically adjusting the port priority through a synaptic plasticity rule, generating a dynamic port strategy matrix; based on the dynamic port strategy matrix, pre-loading a coupon strategy through a memristor array, predicting a user track in combination with a quantum city spatio-temporal model, and generating a real-time push instruction; and executing a real-time push instruction, implanting a topological photonic crystal verification code in the coupon propagation link, verifying the verification authenticity of the user through zero-knowledge proof, and generating a verification certificate chain. According to the method, the environmental noise is eliminated by using the space-time coding characteristics of the pulse neural network, and the multi-source characteristics are fused, so that the problem of characteristic distortion caused by data heterogeneity in edge calculation is solved.

The present invention discloses a method for checking driving conflicts in a Verilog timing module, which includes: scanning Verilog code to obtain at least one always block; parsing each always block statement by statement to obtain statement parsing results, including: register information and driven intervals of registers driven by each statement related to assignment in the Verilog code; constructing a hash table according to the statement parsing results; according to the statement parsing results, taking the union of the driven intervals of the same register belonging to the same always block, and after taking the union, taking the intersection of the driven intervals of the same register belonging to different always blocks to obtain driving conflict intervals; searching the hash table based on the driving conflict intervals to determine statements related to driving conflicts in the Verilog code. The present invention can save the debugging time of users in the RTL design process and improve the development efficiency.

The present disclosure relates to systems and methods for generating communications associated with optimization codes. Generating the communications may include generating the optimization code, which may include: (i) receiving first data associated with one or more of a first computing device and a user of the first computing device; (ii) generating at least two confirmation codes, including one or more of a validation code, a consistency code, and an activity code, which may be associated with a comparative accuracy of the first data, a comparative consistency of the first data, and a comparative activity of the first data, respectively; and (iii) generating the optimization code, which may be based at least in part on the at least two confirmation codes and associated with a relative predictability of the first data.

The invention belongs to the technical field of code completion, and relates to a Verilog row-level code completion method, in particular to a Verilog row-level code completion method based on a non-autoregression model. The method is different from a traditional code completion method based on an autoregression model, the non-autoregression model is used, delay is smaller, and the reasoning speed is remarkably increased. Besides, a sampling strategy guided by mixed grammar is adopted, the method is similar to Teacher Forcing, the sampling size can be dynamically adjusted according to the learning effect of the model, and the method can enable the model to better learn grammar and semantic information in the model so as to improve the code completion accuracy. In conclusion, the invention provides the Verilog code completion method which has relatively high precision and can remarkably improve the reasoning speed at the same time.

The application discloses a kind of verification code digital task identification method, system and equipment based on memristor, it is related to the technical field of memristor, including the following steps: receiving verification code picture training data, verification code picture training data and first memristor array are mapped to obtain read voltage, read voltage and coupling coefficient are matrix multiplied and added, and output current value is obtained;Output current value is converted into voltage pulse, and voltage pulse is input into the second memristor array of storage input data and is calculated by multiplication, and third memristor array is obtained;Read voltage is input into each column device of third memristor array, and the current value corresponding to each column device is obtained, and the current value is input into circuit to obtain voltage value;Voltage value is converted into the first memristor array of programming pulse update coupling coefficient;To coupling coefficient update is completed, and final memristor array is obtained, read voltage and the coupling coefficient of final memristor array are matrix multiplied and added, and output result is obtained, and output result is input into computer and is trained.

The invention provides a c code and verilog code generation method and device, and relates to the technical field of software development and FPGA board card debugging. When the method is executed, firstly, a model is built through GCKontrol modeling software, secondly, floating-point simulation is conducted on the model, thirdly, subsystem packaging is conducted on a module, needing to automatically generate the verilog code, in the model, then the module, needing to automatically generate the verilog code, in a subsystem is calibrated according to a floating-point simulation result, then, the calibrated model is simulated, and finally, the model is subjected to automatic generation of the verilog code. And finally, if the simulation result of the model accords with the expectation, generating a c code and a verilog code at the same time by utilizing the calibrated model. In this way, the c code and the verilog code are automatically generated at the same time.

A dynamic code may be validated by comparing the dynamic code to a verification code. The card may generate the dynamic code using a random object and a function. The random object may be generated using a random object generator. The function may be determinable using a function determination object and a look-up-table (LUT), the function determination object associable to exponents and operators, listed in the LUT, that may be combined with base variables to determine the function. The dynamic code may be determined by substituting portions of the random object for the base variables in the function. The card may communicate the dynamic code, the random object and an identifier to a remote processing facility. The remote processing facility may use the identifier to determine the function, use the random object to determine a verification code and compare the verification code to the dynamic code.

This invention discloses a fast FPGA resource prediction method based on Transformer, comprising the following steps: Step S1: Based on the semantics and types of words in Verilog code, a word segmentation and encoding model is constructed to segment and encode the code, converting the words into word vectors, and generating a word vector sequence that can be input into the Transformer network; Step S2: A sliding window is used to process code inputs of different lengths, and the word vector sequence input by the sliding window is processed through the multi-head self-attention mechanism of the Transformer model to generate a code relevance matrix, representing the relationship between code and hardware resource reuse, and completing feature extraction; Step S3: After performing a convolution operation on the word vectors, they are input into the sliding window again to obtain relevance matrices of different dimensions. After multiple rounds of feature extraction, the features are concatenated and stored in a multi-dimensional feature container, and finally input into a multilayer perceptron to output the resource prediction result. This invention can effectively improve the speed of obtaining the number of FPGA resources.

This invention provides an automated Verilog code generation method and system based on AST (Abstract Syntax Tree) semantic enhancement. The method involves obtaining the Verilog source code, generating a preprocessed version, performing dual verification and pre-screening through compilation and simulation, generating an Abstract Syntax Tree (AST), and extracting key structural information. Semantic enhancement is then performed based on the tree structure of the AST, driven by static analysis. This involves traversing the AST nodes and inferring and labeling semantic information for each node according to heuristic rules, generating a semantically enhanced AST. A training dataset for Verilog code generation is constructed from the Verilog source code, the semantically enhanced AST, and structured semantic hints. A fine-tuned model is then obtained, and finally, Verilog code is generated. Experimental results show that this invention significantly outperforms traditional models in terms of compilation success rate and structural consistency.

The utility model belongs to the technical field of electronic information and communication, and particularly relates to a B code generating device applied to an embedded test environment, which comprises an upper computer and an FPGA (field programmable gate array), the upper computer is connected with the FPGA through a serial port, a system time sending module is arranged in the upper computer, a serial port communication module, a time code protocol analysis module and a B code generating module are arranged in the FPGA, and the B code generating module is connected with the system time sending module. Wherein the B code generation module comprises a time keeping module, a time conversion module and a data processing module; according to the invention, by combining the advantages of the upper computer and the FPGA, a simple and fast B code generating device is designed and realized; meanwhile, the high-speed operation and programmable characteristics of the FPGA are utilized, so that the accuracy and the stability of B code generation are improved; in addition, data interaction between the upper computer and the FPGA is achieved through serial port communication, and the coding accuracy of the B code generating device is conveniently verified.

The invention discloses an information transmission method, device, system and equipment and a medium, which are used for realizing more convenient information transmission between front-end equipment and rear-end equipment of an Internet of Things system. The method suitable for the back-end device provided by the invention comprises the following steps: receiving first information sent by a first front-end device; the first information comprises a first serial number of the first front-end equipment and a first random number generated by the first front-end equipment; determining a pre-generated first parameter based on the first serial number, and generating a first verification code by adopting a first preset algorithm based on the first parameter and the first random number; the first parameter is a parameter which is generated and sent to the first front-end device by the back-end device by adopting a preset rule based on the first serial number in advance; and sending the first verification code to the first front-end equipment, so that the first front-end equipment generates a second verification code by adopting a first preset algorithm based on the first parameter and the first random number, and verifies the rear-end equipment by comparing the first verification code with the second verification code.

A method for designing a time-domain non-stationary V2V MIMO communication channel emulator includes determining basic parameters for the V2V MIMO communication channel; generating a V2V 2D time-domain non-stationary communication channel environment, by using a MATLAB, that is, the numbers of the scatterers and the positions of the scatterers and the like; importing parameters generated in the previous step into a hardware simulation platform to calculate communication channel parameters for clusters, such as an angle distribution and a power distribution, writing a Verilog code for running, and eventually calculating to obtain a channel impulse response of the time-domain non-stationary V2V MIMO communication channel; and comparing with a statistical characteristic of a theoretical communication channel model, and designing an appropriate hardware diagram of a communication channel emulator. The method supports the simulation of time-domain non-stationary V2V MIMO communication channel, filling the gap in the field of communication channel emulators.

The application discloses an abnormal short message behavior detection method and system based on multi-dimensional feature fusion, relates to the related technical field of short message security detection, and comprises the following steps: collecting the space-time distribution features, semantic association graphs and device behavior fingerprints of short message interaction, configuring a dynamic feature pool, and extracting cross-modal feature sequences; performing cascade identification; dynamically adjusting a feature fusion weight matrix, generating an abnormal probability score, triggering a multi-stage verification mechanism when the abnormal probability score exceeds a dynamic abnormal probability threshold; matching the timing mode at an edge computing node, dynamically generating a verification code trigger threshold, and performing interactive risk verification to determine an abnormal short message behavior label. The application solves the technical problems of single detection dimension, difficulty in identifying new complex abnormal short message behaviors, and high false positive and false negative rates in the prior art, and achieves the technical effects of reducing the false positive and false negative rates of short message anomaly detection, improving the detection timeliness and adaptability.

This invention discloses a method and apparatus for multi-port coupon delivery, relating to the field of intelligent marketing technology. The method includes: inputting a multimodal feature tensor into a SNN decision engine, generating SNN synaptic weight parameters based on the spatiotemporal features of user historical behavior, and dynamically adjusting port priorities through synaptic plasticity rules to generate a dynamic port strategy matrix; based on the dynamic port strategy matrix, preloading coupon strategies through a memristor array, and predicting user trajectories using a quantum city spatiotemporal model to generate real-time push instructions; executing the real-time push instructions, and embedding a topological photonic crystal verification code in the coupon propagation chain, verifying the authenticity of user redemption through zero-knowledge proof, and generating a redemption voucher chain. This invention solves the feature distortion problem caused by data heterogeneity in edge computing by utilizing the spatiotemporal coding characteristics of spiking neural networks to eliminate environmental noise and fuse multi-source features.

The application discloses a kind of hardware security vulnerability knowledge graph assisted Verilog security code generation method and device, the method is first according to the natural language description of hardware code generation task input by user, hardware code generation task is decomposed into several subtasks, signal, state conversion and circuit code example are extracted.Second, hardware security vulnerability data is acquired, and hardware vulnerability security knowledge graph is constructed from top to bottom.Then according to the natural language description of subtask, signal, state conversion and circuit code example generates Verilog code.Last, based on hardware vulnerability security knowledge graph, Verilog code is detected and repaired security vulnerability, and generates security Verilog code.The application improves the efficiency and security of hardware code generation, with flexibility and scalability, and reduces implementation complexity.

The invention discloses a knowledge graph auxiliary code generation method oriented to security FSM design, and the method comprises the steps: firstly obtaining an FSM security knowledge document, and constructing an FSM security knowledge graph; secondly, according to the natural language description of the FSM design input by a user, analyzing the security problem existing in the description by using a graph algorithm, outputting a vulnerability list, and according to the FSM security knowledge graph and the vulnerability list, carrying out vulnerability confirmation and security knowledge retrieval, and outputting a security report and a security suggestion. The method comprises the steps that firstly, a code generation task is generated, then, according to natural language description input by a user, the code generation task is decomposed into a plurality of subtasks to generate task plans, then, safety suggestions and the task plans are spliced to output safety task plans, finally, safety Verilog codes are generated according to the safety task plans, and function inspection and safety inspection are conducted. The method improves the security of code generation, has flexibility and expansibility, and is convenient for updating and adding subsequent security knowledge.