Automatic Verilog HDL code generator of parallel CRC (Cyclic Redundancy Check) algorithm and method thereof

Abstract

The invention relates to an automatic Verilog HDL code generator of a parallel CRC (Cyclic Redundancy Check) algorithm and a method thereof. The generator comprises a coefficient generation circuit based on a modelsim simulation platform, a coefficient file C.txt generated by operating a coefficient generation circuit code CG.v and a Verilog code file F.txt generated by operating a Verilog code generation file VG.v. The method comprises the following steps of: (1) extracting design parameters of N, M, A and INT; (2) obtaining the coefficient generation circuit by the design parameters of N, M, A and INT according to the design steps of the coefficient generation circuit; (3) expressing the coefficient generation circuit as CG.v by using the Verilog code; (4) obtaining the coefficient file C.txt by operating the CG.v; and (5) obtaining a Verilog code F.txt of the parallel CRC circuit by operating VG.v. In the invention, the Verilog HDL code generation of the parallel CRC algorithm is simplified.

Description

technical field [0001] The invention relates to a code automatic generator and a method thereof, in particular to a parallel CRC algorithm Verilog HDL code automatic generator and a method thereof. Background technique [0002] Because it is superior to the serial CRC algorithm in terms of speed, the parallel CRC algorithm is widely used in the fields of data transmission, storage, communication, encryption and decryption, etc. When implementing the algorithm with an ASIC and FPGA, the CRC algorithm must first be obtained Verilog HDL code, from which the code further obtains the CRC algorithm netlist through a synthesis tool, thereby obtaining the hardware topology of the CRC algorithm. [0003] The serial CRC circuit has a simple structure and slow operation speed; [0004] The structure of the parallel CRC circuit is complex and the operation speed is fast; [0005] In the serial CRC circuit, if the expression formula 1 of G(X) and the initial value INT of the circuit ar...

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Problems solved by technology

[0016] The object of the present invention is to provide a kind of parallel CRC algorithm Verilog HDL code automatic generator and method thereof, it has solved the complex technical problem that parallel CRC algorithm Verilog HDL code generates in the background technology

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