Verilog coding method achieving ATE test waveform by adoption of FPGA

Abstract

The invention discloses a Verilog coding method achieving ATE test waveform by the adoption of FPGA. Description of a vector period signal set is constructed through task statements, an ATE test period vector is analyzed, and a periodic type set is classified; specific description is conducted on signal behaviors corresponding to all types of periods in the period type set in a vector period signal description set area of Verilog codes, a vector period signal description set is constructed, and period signal waveform is adopted for all period signals in the vector period signal description set to serve as characteristic keywords to be used as an identification naming period description name; Case conditional statements are applied, the number of vector periods serves as the triggering condition of the Case statements, the cycle description name serves as a condition selection object, and the period description name is in linkage with a designated clock period number, so that a vector output list corresponding to ATE test vector description is constructed. By means of the Verilog coding method achieving ATE test waveform by the adoption of the FPGA, efficiency and flexibility of development of converting from the ATE test vector to an FPGA design, development difficulty can be reduced, and design efficiency can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a Verilog encoding method for implementing ATE test waveforms using FPGA. Background technique [0002] FPGA (Field Programmable Gate Array) is usually used for circuit design verification or product customization. Due to its powerful ability to design and implement logic functions, in the field of testing, FPGA is also used to generate specific test waveform vectors to replace professional test systems to implement some test applications. In the application of replacing ATE (automatic test equipment) to realize test waveform output, it is necessary to convert ATE test vector into FPGA design output through hardware description language. The ATE vector waveform has the characteristics of no logical relationship based on the clock cycle and inter-cycle signals. The traditional FPGA hardware description method based on the circuit function description does not reflect th...

AI Technical Summary

Problems solved by technology

The ATE vector waveform has the characteristics of no logical relationship based on the clock cycle and inter-cycle signals. The traditional FPGA hardware description method based on the circuit function description does not reflect the dominant characteristics corresponding to the ATE vector format, resulting in the vector signal description in the verilog code. The readability and editability of the ATE vector conversion are reduced, which brings difficulties to the consistency check and modification editing of ATE vector conversion, resulting in low development efficiency

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