Wafer test structure, wafer, and wafer test method

A wafer test, wafer technology, applied in the field of memory, can solve problems such as insufficient number of pads

Active Publication Date: 2022-07-01
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to provide a wafer test structure, wafer and wafer testing method, by selectively connecting different test devices to corresponding pads when testing different test devices, solving the problem of dicing Insufficient number of pads in slots

Method used

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  • Wafer test structure, wafer, and wafer test method
  • Wafer test structure, wafer, and wafer test method
  • Wafer test structure, wafer, and wafer test method

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Embodiment Construction

[0024] The present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, like elements are designated by like reference numerals. For the sake of clarity, various parts in the figures have not been drawn to scale. Additionally, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be depicted in one figure.

[0025] It will be understood that, in describing the structure of a device, when a layer or region is referred to as being "on" or "over" another layer or region, it can be directly on the other layer or region, or Other layers or regions are also included between it and another layer, another region. And, if the device is turned over, the layer, one region, will be "under" or "under" another layer, another region.

[0026] In order to describe the situation directly above another layer, another area, the expression "directly on" o...

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Abstract

The present application discloses a wafer testing structure, a wafer and a wafer testing method. The method includes: disposing a plurality of bonding pads in a dicing groove of a wafer; disposing at least one testing unit in the dicing groove of the wafer, including a first device and a second device; and testing the first device or the second device , wherein, when the first device is tested, the first device is connected to the corresponding pad, and when the second device is tested, the second device is connected to the corresponding pad. The method solves the problem of insufficient number of pads in the dicing groove by selectively connecting the first device and the second device with the corresponding pads when different test devices are tested.

Description

technical field [0001] The present invention relates to memory technology, and more particularly, to a wafer testing structure, a wafer and a wafer testing method. Background technique [0002] The improvement of the storage density of memory devices is closely related to the advancement of the semiconductor manufacturing process. As the feature sizes of semiconductor manufacturing processes are getting smaller and smaller, the storage density of memory devices is getting higher and higher. In order to further increase the storage density, three-dimensionally structured storage devices (ie, 3D storage devices) have been developed. 3D memory devices include multiple memory cells stacked in a vertical direction, which can exponentially increase the integration level on a wafer per unit area, and can reduce costs. [0003] Existing 3D memory devices are mainly used as non-volatile flash memory. The two main non-volatile flash technologies use NAND and NOR structures, respect...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66H01L23/544
Inventor 陈亮
Owner YANGTZE MEMORY TECH CO LTD
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