Unlock instant, AI-driven research and patent intelligence for your innovation.

Wafer testing method

A wafer test, wafer technology, applied in the wafer test field of embedded flash memory, can solve the problems of interfering with normal chips and disturbing the operation of the chip under test, etc., to reduce crosstalk, reduce the probability of exiting the test mode, and solve misloading Effect

Active Publication Date: 2019-07-16
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
View PDF10 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the existing technology, in order to reduce the test cost and improve the test efficiency, it is necessary to continuously increase the number of simultaneous tests. During the same test, two methods of parallel testing and serial testing are used for testing, but abnormal chips will interfere with normal chips during parallel testing. The idle chip in the serial test will disturb the operation of the chip under test, and as the number of simultaneous tests increases, the problems of crosstalk and synchronization between chips will become more and more serious

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Wafer testing method
  • Wafer testing method
  • Wafer testing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0020] In the wafer testing method of this embodiment, the wafer is tested according to the wafer testing mode, including: when the wafer testing mode is chip parallel testing, if an abnormality is detected in the chip, the power supply of the abnormal chip The pin voltage is set to 0, and then other chips are tested; when the test mode is chip serial testing, the signal pins of other chips to be tested except the chip under test are set to "hold" state, Then the tested chip is detected.

[0021] refer to figure 1 , which is the wafer parallel test flow chart of Embodiment 1 of the present invention. The wafer parallel test includes four chips, namely chip 1, chip 2, chip 3 and chip 4, wherein chip 4 is an abnormal chip, and its The power pin voltage is set to 0.

[0022] refer to figure 2 , which is the wafer serial test flow chart of Embodiment 1 of the present invention. The wafer serial test includes four chips, namely chip 1, chip 2, chip 3 and chip 4, chip 1, chip 2 ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a wafer testing method, which comprises the following steps of: when chips on a tested wafer are tested in parallel, and when the chips are abnormal, setting the voltage of a power supply pin of an abnormal chip to be 0v, so as to reduce the testing interference of the abnormal tested chip on a normal tested chip; in the chip serial test process on the tested wafer, when a chip is in an idle state, setting a signal pin of the idle tested chip in a'hold 'state, so as to reduce the probability that the idle tested chip exits from a test mode. According to the wafer testingmethod, crosstalk between chips can be effectively reduced, the false load rate in the testing process is reduced, the testing stability is improved, and the yield of wafers is increased.

Description

technical field [0001] The invention relates to the field of integrated circuit testing, in particular to a wafer testing method for embedded flash memory. Background technique [0002] Wafer testing (Circuit Probing, CP), also known as circuit needle testing, directly tests the chip die (die) on the wafer (wafer) before packaging to verify whether each chip meets product specifications. In the existing technology, in order to reduce the test cost and improve the test efficiency, it is necessary to continuously increase the number of simultaneous tests. During the same test, two methods of parallel testing and serial testing are used for testing, but abnormal chips will interfere with normal chips during parallel testing. The idle chip in the serial test will disturb the operation of the chip under test, and as the number of simultaneous tests increases, the problems of crosstalk and synchronization between chips will become more and more serious. Contents of the invention...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G11C29/00G11C29/56
CPCG11C29/006G11C29/56
Inventor 任栋梁
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP