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A wafer testing method

A wafer test, wafer technology, applied in the wafer test field of embedded flash memory, can solve the problems of disturbing the operation of the chip under test and disturbing the normal chip, etc., to reduce crosstalk, solve misloading, and reduce the probability of exiting the test mode Effect

Active Publication Date: 2021-08-27
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the existing technology, in order to reduce the test cost and improve the test efficiency, it is necessary to continuously increase the number of simultaneous tests. During the same test, two methods of parallel testing and serial testing are used for testing, but abnormal chips will interfere with normal chips during parallel testing. The idle chip in the serial test will disturb the operation of the chip under test, and as the number of simultaneous tests increases, the problems of crosstalk and synchronization between chips will become more and more serious

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Embodiment 1

[0020] In the wafer testing method of this embodiment, the wafer is tested according to the wafer testing mode, including: when the wafer testing mode is chip parallel testing, if an abnormality is detected in the chip, the power supply of the abnormal chip The pin voltage is set to 0, and then other chips are tested; when the test mode is chip serial testing, the signal pins of other chips to be tested except the chip under test are set to "hold" state, Then the tested chip is detected.

[0021] refer to figure 1 , which is the wafer parallel test flow chart of Embodiment 1 of the present invention. The wafer parallel test includes four chips, namely chip 1, chip 2, chip 3 and chip 4, wherein chip 4 is an abnormal chip, and its power supply The pin voltage is set to 0.

[0022] refer to figure 2 , which is the wafer serial test flow chart of Embodiment 1 of the present invention, the wafer serial test includes four chips, respectively chip 1, chip 2, chip 3 and chip 4, ch...

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Abstract

The invention provides a wafer testing method. When the chips on the tested wafer are tested in parallel, when the chip is abnormal, the power supply pin voltage of the abnormal chip is set to 0v, so as to reduce the abnormality of the tested chip. Normal test interference of the tested chip; during the serial test of the chips on the tested wafer, when a chip is in an idle state, the signal pins of the idle tested chip are set to the "hold" state to reduce the The probability of an idle chip under test exiting test mode. The wafer testing method can effectively reduce the crosstalk between chips, reduce the false load rate in the test, improve the stability of the test, and improve the yield rate of the wafer.

Description

technical field [0001] The invention relates to the field of integrated circuit testing, in particular to a wafer testing method for embedded flash memory. Background technique [0002] Wafer testing (Circuit Probing, CP), also known as circuit needle testing, directly tests the chip die (die) on the wafer (wafer) before packaging to verify whether each chip meets product specifications. In the existing technology, in order to reduce the test cost and improve the test efficiency, it is necessary to continuously increase the number of simultaneous tests. During the same test, two methods of parallel testing and serial testing are used for testing, but abnormal chips will interfere with normal chips during parallel testing. The idle chip in the serial test will disturb the operation of the chip under test, and as the number of simultaneous tests increases, the problems of crosstalk and synchronization between chips will become more and more serious. Contents of the invention...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/00G11C29/56
CPCG11C29/006G11C29/56
Inventor 任栋梁
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP