Chip testing system and method based on fpga

Abstract

The invention discloses an fpga-based chip testing system and method, and relates to the technical field of chip testing. A chip test system based on fpga, including PC end and fpga, PC end is used for applying test stimulation instruction, and test stimulation instruction is sent to fpga; Said fpga is used for receiving test stimulation instruction and sending to chip after parsing, so The fpga can determine whether the test type is an IO test or a register test, the IO test includes the configuration of the chip test mode and the operation of chip IO pull-up and pull-down, and the register test includes read and write operations on the chip registers. The invention supports two test types of IO and register read and write operations, users can debug test codes online, the compilation time is short, and various chip test requirements can be flexibly met.

Description

technical field [0001] The invention relates to the technical field of chip testing. Background technique [0002] Chip test modes usually include scan, bist, analog, and IO (input / output) test modes, and different test modes correspond to different test purposes. The current chip test platform is generally based on ATE (automatic test equipment). After configuring the test mode for a specific chip test IO pin, apply a test stimulus to the chip IO, read the value given by the chip IO and compare it with the correct value. The conclusion of whether the chip is normal. However, due to the relatively expensive experimental equipment of ATE testing machines, it is difficult for ordinary laboratories to have similar testing equipment and environments. Moreover, in the traditional test mode, many tests pull the test signal to the I / O of the chip, which not only increases the complexity of the chip design for testability (DesignForTest, DFT), but also makes the I / O limited Or wh...

AI Technical Summary

Problems solved by technology

However, due to the relatively expensive experimental equipment of ATE testing machines, it is difficult for ordinary laboratories to have similar testing equipment and environments.

Moreover, in the traditional test mode, many tests pull the test signal to the I / O of the chip, which not only increases the complexity of the chip design for testability (DesignForTest, DFT), but also makes the I / O limited Or when it comes to high-speed analog (analog) IP test chips, many tests cannot be realized, because it is not impossible to put all the test signals on the chip IO pins

[0003] At the same time, in the chip test mode, traditional software debugging methods cannot be used, so it is an urgent problem to provide a low-cost, high-efficiency, and flexible configuration test system to meet the test requirements for chips.

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