AES encryption circuit based on two-way complementary structure and capable of detecting errors

An encryption circuit and circuit technology, applied in electrical digital data processing, instruments, digital data authentication, etc., can solve problems such as error injection attacks and inability to defend against power consumption attacks, and achieve the effect of defending against power consumption attacks and error injection attacks

Active Publication Date: 2019-07-26
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

[0008] The technical problem to be solved by the present invention is to provide an error-detectable AES encryption circuit based on a two-way complementary structure, which can solve the problem that the existing AES encryption circuit cannot defend Problems with Power Consumption Attacks and Fault Injection Attacks

Method used

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  • AES encryption circuit based on two-way complementary structure and capable of detecting errors
  • AES encryption circuit based on two-way complementary structure and capable of detecting errors
  • AES encryption circuit based on two-way complementary structure and capable of detecting errors

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Embodiment Construction

[0022] Such as figure 1 As shown, an error-detectable AES encryption circuit based on a two-way complementary structure, the input plaintext and the output ciphertext C' are both 128-bit data packets, and the key is the number of key bits specified in the AES standard, including N r (N r The number of round transformation operations specified in the AES standard) complementary round transformation units (complementary round transformation 1, complementary round transformation 2, ..., complementary round transformation N r ), the input of complementary round transformation 1 is the data obtained by XOR operation with the initial key after bitwise inversion of the input plaintext, the 1st to the Nth r-1 round of complementary round transformation unit has the same structure, and is composed of complementary byte replacement unit, complementary row shift unit, complementary column mixing unit and complementary key adding unit connected in sequence; Nth r The round-complementary...

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Abstract

The invention discloses an AES encryption circuit based on a two-way complementary structure and capable of detecting errors. The AES encryption circuit comprises a key expansion unit, a conventionalAES encryption circuit unit, a complementary AES encryption circuit unit and a selector. The AES encryption circuit provided by the invention not only can defend power consumption attacks, but also can defend error injection attacks. By designing the complementary AES encryption unit, the Hamming weight of the data in the circuit is kept unchanged when the circuit processes different data. A judgment is made as to whether the encryption circuit is abnormal or not according to the result value of the output of the conventional AES encryption circuit unit and the result value of the output of the complementary AES encryption circuit unit after XOR operation. Accordingly, the output of the selector is controlled, and a wrong injection attack is effectively defended.

Description

technical field [0001] The invention relates to the technical field of encryption circuit realization, in particular to an error-detectable AES encryption circuit based on a two-way complementary structure. Background technique [0002] Advanced Encryption Standard (AES), also known as Rijndael encryption, was designed by Belgian cryptographers Joan Daemen and Vincent Rijmen. It is a new generation of block symmetric cipher formulated by the National Institute of Standards and Technology in 2001. Algorithm, used to replace the original Data Encryption Standard (DataEncryption Standard, DES). The AES cipher algorithm is an iterative, symmetric block cipher algorithm with a data packet length of 128 bits and a key length of 128, 192, and 256 bits. According to these three different key lengths, the encryption process requires 10, 12, and 14 rounds of round transformation operations, and each round transformation operation includes four sub-operations: byte replacement, row sh...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/60G06F21/46
CPCG06F21/602G06F21/46
Inventor 张金宝吴宁葛芬周芳张肖强黎建华闫改珍谢海燕
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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