Synchronization control circuit for display
A technology for synchronous control and control circuits, applied in static indicators, instruments, etc., to solve problems such as time difference, line tearing, and incorrect opening of display elements
Active Publication Date: 2019-10-29
ACER INC
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Problems solved by technology
However, the traditional bridge circuit is not asynchronous when using different data channels to transmit part of the display data to the timing controller, but there will be a time difference
If the time difference between the partial display data of different data channels sent to the timing controller exceeds a predetermined threshold, the partial display data of each data channel received by the timing controller will be out of sync, which will cause the display on the display panel Components are turned on incorrectly, for example, red, green, or blue lines will be generated on the display panel, which means that there is line tearing (linetearing)
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[0033] In order to make the above-mentioned purpose, features and advantages of the present invention more comprehensible, a preferred embodiment will be exemplified below and described in detail with accompanying drawings.
[0034] figure 1 is a block diagram showing a display system according to an embodiment of the present invention. In one embodiment, the display system 100 includes a host 110 , a bridge circuit 120 , buffers 121 and 122 , a control circuit 123 , a timing controller 150 , and a display panel 160 . The host 110 can be, for example, a personal computer, and can transmit display data (such as RGB pixel data) to the bridge circuit 120 through a transmission interface (such as a DisplayPort (DisplayPort) interface). The bridge circuit 120 converts the received display data into a plurality of partial display data conforming to the display serial interface of the mobile industry processor interface, wherein each part of the display data is stored in the corresp...
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The invention provides a synchronization control circuit for a display. The synchronization control circuit comprises: a plurality of buffers, wherein the buffers are used to store a plurality of partial display data from different data channels in a bridge circuit; and a control circuit used to control the data writing and data reading of each buffer. The control circuit is based on a data readysignal output from a specific buffer in the buffers to control the buffer to output the stored display data to one or more timing controllers in a display at the same time, this allows the one or moretiming controllers to simultaneously scan different parts of the same horizontal line on a display panel of the display at the same time.
Description
technical field [0001] The invention relates to a control circuit, in particular to a synchronous control circuit for a display. Background technique [0002] In the traditional bridge circuit, the display data can be received by the main control terminal, and converted into the display data of the display serial interface (Display Serial Interface, DSI) of the mobile industry processor interface (Mobile Industry Processor Interface, MIPI), and output to Timing controller for the display panel. However, the traditional bridge circuit uses different data channels to transmit part of the display data to the timing controller at a time that is not asynchronous, but has a time difference. If the time difference between the partial display data of different data channels sent to the timing controller exceeds a predetermined threshold, the partial display data of each data channel received by the timing controller will be out of sync, which will cause the display on the display p...
Claims
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Login to View More IPC IPC(8): G09G3/3208G09G3/36
CPCG09G3/3208G09G3/36
Inventor 黄榆君邱佳瑯陈志诚
Owner ACER INC