A method for preparing three-dimensional superstretchable crystalline nanowires

A nanowire and crystalline technology, applied in the field of preparing three-dimensional ultra-stretchable crystalline nanowires, can solve the problems of reduced relaxation space, nanowire breakage, limitation, etc., and achieves a large relaxation space and a relaxable space. More, the effect of improving stretchability

Active Publication Date: 2022-06-21
NANJING UNIV
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Problems solved by technology

[0003] However, the natural rigidity of many materials severely limits the emerging new flexible and stretchable electronic devices. Therefore, it is very important to control the morphology of crystalline nanowires to make them super stretchable.
Since the planar crystalline nanowires are greatly constrained by the substrate, the relaxation space is reduced, and it is very easy to cause the nanowires to be broken during the stretching process, making it difficult to prepare reliable flexible electronic devices.

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  • A method for preparing three-dimensional superstretchable crystalline nanowires
  • A method for preparing three-dimensional superstretchable crystalline nanowires
  • A method for preparing three-dimensional superstretchable crystalline nanowires

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Embodiment Construction

[0027] In order to make the technical solutions and advantages of the present invention clearer, the present invention will be further elaborated below in conjunction with specific implementation examples. The flow chart is as follows figure 1 shown.

[0028] The steps are as follows: 1) Use silicon wafers, glass, aluminum foil, compounds (such as silicon nitride, silicon oxide, silicon oxynitride), polymers or other metal materials as substrates, and use PECVD or PVD processes to deposit on the substrates An insulating dielectric layer (about 4 μm); 2) Use photolithography, electron beam direct writing or mask technology to define the pattern of the step edge, use inductively coupled plasma (ICP) etching or reactive plasma etching (RIE) The process etches the dielectric layer to form a vertical step sidewall (about 1 μm depth); use ICP or RIE alternate cycle etching method to etch the step structure; first use C in the etching process 4 f 8 、CF 4 , SF 6 Reactive gases wit...

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Abstract

A method for preparing three-dimensional super-stretchable crystalline nanowires, 1) using PECVD or PVD to deposit a layer of insulating dielectric layer on the substrate as a sacrificial layer, 2) using photolithography and electron beam direct writing to define periodic step edges pattern, use dry or wet alternate etching process to etch the dielectric layer to form vertical step sidewall; 3) treat the step surface with corrosive liquid to form wavy steps; 4) photolithography electron beam direct writing or mask plate again Technical definition The pattern perpendicular to the step and the etching technology are used to prepare the secondary guide channel perpendicular to the step; 5) A strip-shaped catalytic metal layer is locally deposited by photolithography, evaporation or sputtering; 6) Catalytic The metal layer is converted into separated metal nanoparticles; 7) The temperature is lowered below the melting point of the catalytic metal particles, and the entire structure surface is deposited to cover the amorphous semiconductor precursor thin film layer; the crystalline nanowires are deposited; the nanowires will be along the Guided channel growth of wavy steps.

Description

technical field [0001] The invention relates to a method for obtaining super-stretchable crystalline nanowires (nanowire) by channel guiding technology, in particular to a method for forming large-area, easy-to-locate wave-shaped guiding channels by using two etching processes. Background technique [0002] Semiconductor crystalline silicon nanowire (Nanowire) is the core material of modern microelectronics technology due to its high carrier mobility and the ability to achieve efficient, stable and reliable doping processes. Here, the inventor of the present application is the earliest A planar solid-liquid-solid (IP SLS) growth mode is proposed, in which amorphous silicon is used as a precursor, and crystalline silicon nanowire structures are grown by absorbing amorphous silicon with low melting point metal indium and tin nanoparticles. At the same time, three-dimensional nano-steps can be prepared by using two-time etching technology, and the steps are used as a guide. The...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): H01L21/02B82Y40/00
CPCH01L21/02532H01L21/02603H01L21/02592H01L21/0262H01L21/02672B82Y40/00
Inventor余林蔚孙莹董泰阁王军转
OwnerNANJING UNIV