Storage unit and application of low-power static random access memory

Abstract

The invention provides a storage unit of a new type of static random access memory with low power consumption, which is characterized in that it includes five word lines and four bit lines, and the five word lines are word line 1, word line 2, word line 3, word line 3 and word line 3 respectively. Line 4 and word line 5, the four bit lines are bit line 1, bit line 2, bit line 3 and bit line 4 respectively. Compared with the most advanced technology, the structure of the present invention reduces the energy consumption to 24.5% of the original, and has the following advantages: using the feature that the cmos channel current and the gate voltage are positively correlated, and using a set of analog voltage values ​​as The result of a gate voltage-driven SRAM is that, for the same turn-on time, the analog value of the voltage on the bit line represents the result of the multiplication.

Description

technical field [0001] The invention relates to a storage unit of a two-bit by two-bit low-power static random access memory based on input data, and also relates to an application structure of the above-mentioned SRAM storage unit. Background technique [0002] The in-memory computing unit based on input data is a storage unit of a new type of static random access memory that realizes multi-bit multiplication of in-memory computing. In traditional computer architectures, operations on data require multiple clock cycles and require significant additional power consumption. The in-memory calculation method enables the storage unit to have the function of operation at the same time, and the calculation result is directly read out during the reading process. In the in-memory operation mode, there is a trade-off between output accuracy and power consumption. The read speed of in-memory computing should be close to the read speed of traditional memory. [0003] The implementat...

AI Technical Summary

Problems solved by technology

[0013] The disadvantage of the digital method is that it requires more than one clock cycle, for example, a four-bit addition operation requires four clock cycles, and a two-bit multiplication requires seven clock cycles

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