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Test Methods for Standard Cell Libraries

A technology of standard cell library and test method, applied in electronic circuit testing, measuring electricity, measuring devices, etc., can solve the problems of many test vectors and low work efficiency

Active Publication Date: 2021-12-17
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a test method of a standard cell library to solve the problems of many test vectors and low work efficiency

Method used

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  • Test Methods for Standard Cell Libraries
  • Test Methods for Standard Cell Libraries
  • Test Methods for Standard Cell Libraries

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Experimental program
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Embodiment Construction

[0046] The testing method of the standard cell library proposed by the present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0047] Please refer to image 3 , the embodiment of the present invention provides a method for testing a standard cell library, comprising the following steps:

[0048] Step S1: providing a standard cell library, the standard cell library includes combinational logic cells and sequential logic cells;

[0049] Step S2: inputting a test signal to the combinational logic unit and the sequential logic unit to obtain an output signal of the combinational logic ...

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Abstract

The invention provides a test method of a standard cell library, in the test method of the standard cell library, by inputting test signals to the combinational logic unit and the sequential logic unit, the output signal and timing of the combinational logic unit are obtained Logic unit output signal; respectively select the data in the combinational logic unit output signal and the sequential logic unit output signal; and compare the selected data in the combinational logic unit output signal with a combinational logic test data, and The selected data in the output signal of the sequential logic unit is compared with a sequential logic test data to test whether the functions of the combinational logic unit and the sequential logic unit are normal. Therefore, the functions of the combinational logic unit and the sequential logic unit are tested by setting the test signal, thereby reducing test vectors and improving work efficiency.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a testing method of a standard cell library. Background technique [0002] Today's testing method for standard cell libraries is to divide combinational logic cells and sequential logic cells into two modules. The port types of the two modules are the same and can share the input terminal, but different test signals are given to the two modules for testing. Existing test method, when testing the combinational logic unit, sets 2 to the unit that has n ports n test vectors. Such as figure 1 As shown, test signal 01, output signal 02, if it is a standard cell library composed of 100 units, 60 of which are combinatorial logic units, then it is necessary to set 60*2 n a test vector. Such as figure 2 As shown, the existing method is to input the test signal 01 when the function of the sequential logic unit is tested, and when the clock signal 03 is input, the u...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28
CPCG01R31/2853
Inventor 尤美琳高唯欢胡晓明
Owner SHANGHAI HUALI MICROELECTRONICS CORP