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Standard cell library test method

A technology of standard cell library and test method, which is applied in the direction of electronic circuit test, measuring circuit, measuring device, etc., and can solve the problems of many test vectors and low work efficiency

Active Publication Date: 2020-04-10
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a test method of a standard cell library to solve the problems of many test vectors and low work efficiency

Method used

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Embodiment Construction

[0046] The testing method of the standard cell library proposed by the present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0047] Please refer to image 3 , the embodiment of the present invention provides a method for testing a standard cell library, comprising the following steps:

[0048] Step S1: providing a standard cell library, the standard cell library includes combinational logic cells and sequential logic cells;

[0049] Step S2: inputting a test signal to the combinational logic unit and the sequential logic unit to obtain an output signal of the combinational logic ...

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Abstract

The invention provides a standard cell library test method. The standard cell library test method comprises the steps of: inputting a test signal to a combinational logic unit and a time sequence logic unit so as to obtain a combinational logic unit output signal and a time sequence logic unit output signal; respectively selecting data in the combinational logic unit output signal and the time sequence logic unit output signal; and comparing the data selected from the combinational logic unit output signal with combinational logic test data, and comparing the data selected from the time sequence logic unit output signal with time sequence logic test data so as to test whether the functions of the combinational logic unit and the time sequence logic unit are normal or not. Therefore, the functions of the combinational logic unit and the time sequence logic unit are tested by setting the test signal, so that the test vector is reduced, and the working efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a testing method for a standard cell library. Background technique [0002] The current test method for standard cell libraries is to divide the combinational logic unit and sequential logic unit into two modules. The ports of these two modules are of the same type and can share the input end, but they are respectively given different test signals for testing. The existing test method sets 2 for the unit with n ports when testing the combinational logic unit n test vectors. like figure 1 As shown, test signal 01, output signal 02, if it is a standard cell library composed of 100 cells, of which 60 are combinational logic cells, then set 60*2 n test vectors. like figure 2 As shown, the existing method is to input the test signal 01 when the function of the sequential logic unit is tested, and when the clock signal 03 is input, the unit with the set and res...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
CPCG01R31/2853
Inventor 尤美琳高唯欢胡晓明
Owner SHANGHAI HUALI MICROELECTRONICS CORP