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Design and test method of a boundary scan test link

A technology of boundary scan test and test method, applied in the direction of measuring electricity, measuring device, measuring electrical variables, etc., can solve problems such as unsatisfactory realization, improve fault coverage and fault detection rate, reduce test vectors, and improve test efficiency Effect

Active Publication Date: 2020-10-16
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Design and test method of a boundary scan test link
  • Design and test method of a boundary scan test link
  • Design and test method of a boundary scan test link

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[0030] figure 1 It is a flow chart of the design and test method of a boundary scan test link in the present invention.

[0031] In this example, if figure 1 Shown, the design of a kind of boundary scan test link of the present invention and testing method comprise the following steps:

[0032] S1. Design the boundary scan test link and add it to the circuit board under test

[0033] In a large and complex digital circuit board, there are many devices of different types, different manufacturers and different starting voltages, and they are interconnected to form small modules with different functions. For this, we can use this functional whole to ensure The design of the scanning link is carried out under the premise of the coverage rate; we will describe the specific process of the design below.

[0034] S1.1. Analyze the pin utilization rate of each digital chip on the tested circuit board, that is, the idle rate of the pins, and divide the digital chips with low pin util...

example

[0046] In this example, if figure 2 As shown, first divide the entire complex digital circuit board into modules, and divide several or even more digital chips with low utilization rate into different functional modules Mx according to their realized functions. In this way, the circuit board includes a single digital IC chips and functional modules Mx, and then connect these digital IC chips and functional modules Mx to form a boundary scan test link through a common test link connection method. figure 2 M1, M2, and M3 in are different functional modules, which contain multiple digital chips that may contain BS units or not contain BS units. The specific connection method of the boundary scan test link is as follows: the entire test link connects IC chips in series into one or more test links, and the JTAG signal composed of TDI, TDO, TCK, and TMS is also connected to each M module. Modules perform individual boundary-scan tests. figure 2 Only two signal lines TDI and TDO...

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Abstract

The invention discloses a design and test method of a boundary scan test link. Firstly, the designed boundary scan test link is added to a circuit board to be tested, and then digital chips with low pin utilization rates in the circuit board to be tested are implemented according to the Functions are divided into different functional modules, which are connected by boundary scan test link to form a complete boundary scan test link. Finally, classify the boundary scan test link to find out the specific fault type and fault location , and display the results.

Description

technical field [0001] The invention belongs to the technical field of electronic circuit fault testing, and more specifically relates to a design and testing method of a boundary scan testing link. Background technique [0002] In February 1990, the Joint Test Action Group (JTAG) and the IEEE committee jointly proposed the IEEE 1149.1-1990 standard. After years of improvement and supplementation, the IEEE 1149.1-2001 standard was finally formed. The test technique defined by the standard is the boundary-scan test technique. [0003] Boundary scan test technology is proposed to solve the test problems of new electronic devices such as VLSI (Very Large Scale Integration). This technology can judge and locate the fault of the circuit board by reading the pin data of the chip on the circuit board when the traditional test technology cannot detect the fault of the large-scale integrated circuit and thus fails to meet the test requirements. It can not only detect individual ch...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3185
CPCG01R31/318533G01R31/318583
Inventor 刘震昌磊杨成林黄建国周秀云
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA