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Multiplier, data processing method, chip and electronic device

A multiplier and processing device technology, applied in the field of computers, can solve the problems of increasing the delay of compression circuits, reducing the overall performance of multiplier computing performance chips, etc.

Active Publication Date: 2022-06-17
SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, in most traditional technologies, in the process of processing partial product compression, the use of Wallace tree circuits will increase the delay of the compression circuit, thereby reducing the operational performance of the multiplier and the overall performance of the chip.

Method used

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  • Multiplier, data processing method, chip and electronic device
  • Multiplier, data processing method, chip and electronic device
  • Multiplier, data processing method, chip and electronic device

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Embodiment Construction

[0055] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

[0056] The multiplier provided by this application can be applied to AI chips, Field-Programmable Gate Array (FPGA) chips, or other hardware circuit devices to perform multiplication processing. The specific structure diagram is as follows: figure 1 shown.

[0057] figure 1 A structure diagram of a multiplier is provided for one embodiment. like figure 1 As shown, the multiplier includes: an encoding circuit 11, a compression tree group circuit 12 and an accumulation circuit 13; the output end of the encoding circuit 11 is connected to the input end of the compressi...

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Abstract

The application provides a multiplier, a data processing method, a chip and electronic equipment, the multiplier includes: an encoding circuit, a compression tree group circuit, and an accumulation circuit; the output end of the encoding circuit and the input of the compression tree group circuit The output end of the compression tree group circuit is connected to the input end of the accumulation circuit, and the multiplier can compress the partial product of the target code through the compression tree group circuit, effectively reducing the compression circuit in the multiplier. delay, thereby improving the computing performance of the multiplier and the overall performance of the chip.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a multiplier, a data processing method, a chip and an electronic device. Background technique [0002] With the continuous development of digital electronic technology, the rapid development of various artificial intelligence (Artificial Intelligence, AI) chips has higher and higher requirements for high-performance digital multipliers. Neural network algorithm, as one of the algorithms widely used in smart chips, multiplication operation through multipliers is a common operation in neural network algorithms. [0003] Most of the traditional multipliers use the Booth algorithm to obtain the partial product, compress the partial product through the Wallace tree circuit, and then accumulate the compressed result through a set of carry-ahead adders and output the final result. [0004] However, in most conventional technologies, in the process of processing partial produc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/52G06N3/063
CPCG06F7/52G06N3/063
Inventor 不公告发明人
Owner SHANGHAI CAMBRICON INFORMATION TECH CO LTD