Method and system for reducing over-erase phenomenon of NAND flash memory, storage medium and terminal

A storage medium and over-erasing technology, applied in information storage, static memory, read-only memory, etc., can solve the problems of over-erasing, affecting chip operation, etc., so as to avoid over-erasing and reduce the phenomenon of over-erasing. Effect

Pending Publication Date: 2020-10-16
XTX TECH INC
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  • Claims
  • Application Information

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Problems solved by technology

[0006] The object of the present invention is to provide a method, system, storage medium and terminal for reducing the over-erasing phenomenon of non-type flash memory, aiming at solving the over-erased phenomenon existing in the Nor flash memory, affecting the problem of chip operation

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  • Method and system for reducing over-erase phenomenon of NAND flash memory, storage medium and terminal
  • Method and system for reducing over-erase phenomenon of NAND flash memory, storage medium and terminal
  • Method and system for reducing over-erase phenomenon of NAND flash memory, storage medium and terminal

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Embodiment Construction

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of them. The components of the embodiments of the application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations. Accordingly, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.

[0035] It should ...

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Abstract

The invention discloses a method and a system for reducing an over-erase phenomenon of a non-flash memory, a storage medium and a terminal. The method comprises the following steps of: simultaneouslyselecting cells on all word lines in an area to be erased and executing an erase operation; checking the word lines one by one according to a word line numbering sequence, judging whether all cells onthe current word line are successfully erased or not, and continuing to check the next word line if all the cells are successfully erased; and if the cells on the currently-checked word line are notsuccessfully erased, re-erasing the cells on the currently-checked word line until all the cells on the currently-checked word line are successfully erased, and continuing to check the next word line.By the adoption of the method, even if cells difficult to erase exist and can be successfully erased after multiple times of erasing, cells on other word lines cannot be over-erased during multiple times of erasing, and therefore the phenomenon that cells on other word lines are over-erased is avoided.

Description

technical field [0001] The invention relates to the field of IC design, in particular to a method, system, storage medium and terminal for reducing the over-erasing phenomenon of non-type flash memory. Background technique [0002] Nor flash memory has three main operations, the first is the read operation (Read), the second is the write operation (Program), and the third is the erase operation (Erase). [0003] The erase unit of traditional nor flash is divided into sector erase (sector erase), block erase (block erase) and chip erase (full chip erase). A sector generally consists of 4 or 8 word lines, such as figure 1 shown. A block usually consists of 8 or 16 sectors, such as figure 2 shown. The traditional block erase method is to select all word lines contained in all sectors in this block at the same time. Take a block consisting of 16 sectors as an example. During the block erase process, 4x16=64 word lines will be selected at the same time, and all selected wor...

Claims

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Application Information

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IPC IPC(8): G11C16/34G11C16/14
CPCG11C16/14G11C16/3477
Inventor 张柱定王振彪高益
Owner XTX TECH INC
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