A time stamp jitter compensation method and device

Abstract

The embodiment of the present invention provides a time stamp jitter compensation method and device. The method includes: based on the 1588 clock, performing clock synchronization on the time stamp sampling identification signal in the first system clock domain to obtain the time stamp sampling identification signal in the 1588 clock domain; Based on the system clock, clock synchronization is performed on the time stamp sampling identification signal of the 1588 clock domain to obtain the time stamp sampling identification signal of the second system clock domain; according to the time stamp sampling identification signal of the first system clock domain and the second The time stamp sampling in the system clock domain identifies the interval period between signals, and performs time stamp delay compensation. A time stamp jitter compensation method and device provided by the embodiments of the present invention effectively compensates the jitter of the time stamp by amplifying the error caused by the synchronization of the time stamp sampling identification signal in the system clock domain, and then performing identification and compensation.

Description

technical field [0001] The present invention relates to the technical field of time synchronization, in particular to a time stamp jitter compensation method and device. Background technique [0002] With the advent of the 5G communication era, 5G communication poses new requirements and challenges for time synchronization technology, and improving the accuracy of time stamps is the key to meeting new requirements. [0003] When processing timestamps, there is a conversion problem from the timestamp sampling identification signal in the system clock domain or the local clock domain to the timestamp sampling identification signal in the 1588 clock domain. For the 125MHz 1588 clock, the clock domain conversion error of the timestamp sampling identification signal is ±8ns, this error will cause the jitter of the time stamp, and then affect the performance of time synchronization. [0004] In the prior art, the time stamp jitter compensation methods include increasing the frequ...

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Problems solved by technology

[0006] In order to solve the problem that the time stamp jitter is caused by the ±8ns clock domain conversion error between the time stamp sampling identification signal in the system clock domain or the local clock domain and the time stamp sampling identification signal in the 1588 clock domain, the embodiment of the present invention provides a method to overcome the above problems or at least A Time Stamp Jitter Compensation Method and Device Partially Solving the Problems Above

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