Compression method of convolutional neural network and implementation circuit thereof

Abstract

The invention provides a compression method of a convolutional neural network and an implementation circuit thereof. The method comprises the following steps: (1) dividing the convolutional neural network into a non-pruning layer and a pruning layer; (2) pruning the whole convolutional neural network, and then retraining to obtain a high-precision sparse network; (3) removing the weight mask of the non-pruning layer; (4) progressively quantifying the pruning layer; and (5) keeping the weight of the pruning layer unchanged, and performing linear quantization on the non-pruning layer to obtain acompressed convolutional neural network. According to the compression method, the convolutional neural network model can be greatly compressed under the condition of ensuring high processing performance. Aiming at the compression method, the invention further provides an implementation circuit of the convolutional neural network, the implementation circuit comprises a distributed non-pruning layer hardware processing circuit and a pruning layer hardware processing circuit, the two circuits jointly implement the convolutional neural network in an assembly line mode so as to form an assembly line processing mode, and the processing performance is greatly improved.

Description

technical field [0001] The invention relates to the field of deep learning accelerator design, in particular to a convolutional neural network compression method and an implementation circuit thereof. Background technique [0002] With the rapid development of convolutional neural networks in target detection and recognition, it is possible to greatly improve the accuracy of image recognition and detection. However, in order to achieve better target detection and recognition performance, the convolutional neural network is continuously deepened, which brings about a rapid increase in the amount of calculation and expansion of the model size. Therefore, convolutional neural networks need parallel devices to accelerate them, save training time or meet the requirements of real-time object detection, such as high-power GPU devices. In order to realize the deployment of deep convolutional neural networks on low-power embedded devices, FPGA-based convolutional neural network acce...

AI Technical Summary

Problems solved by technology

However, a large number of studies have shown that due to the model irregularity caused by the pruning algorithm, the parallel computing efficiency of the neural network is low, which has a serious impact on its processing speed.

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