Direct memory access system and method

Abstract

A direct memory access (DMA) system and method are provided, the system comprising: a DMA memory configured to cache data; a memory configured to store data; a DMA storage indexer configured to determine whether a write address is an address frequently accessed by a central processing unit (CPU) or not in response to a write command of DMA equipment for writing data into the write address; if it is determined that the write address is an address frequently accessed by a CPU, caching data to be written in the DMA memory; and if it is determined that the write address is not the address frequently accessed by the CPU, sending data to be written to the memory for storage.

Description

technical field [0001] The present application relates to the field of integrated circuits, and more particularly, to a direct memory access (Direct Memory Access, DMA) system and a direct memory access DMA method. Background technique [0002] The early CPU storage hierarchy is three layers, namely CPU registers, DRAM main memory (or memory) and disk storage. Because the access time overhead between the register and the main memory is very different, the designer added an L1 cache (2 to 4 clock cycles) between the register (one clock cycle) and the main memory, for example, when the CPU needs to read from the main memory When the data with address A is fetched from the memory, the address A is first sent to the cache. When the CPU requests to access the data at address A, if the data with address A is stored in the cache (that is, a cache hit occurs), it is directly read from the cache. The data is taken out and passed to the CPU. In this way, the data frequently accessed...

AI Technical Summary

Problems solved by technology

At this time, if CPU core 1 needs to access the value of x again, but there is a value of x in the cache at this time, the value obtained by CPU core 1 is the old value of 0, and the cache is inconsistent.

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