Random instruction sequence generation method based on data correlation constraints

Abstract

The invention discloses a data correlation constraint-based random instruction sequence generation method. The method comprises the following steps of S1, performing information extraction on an instruction set; s2, if the number of the generated instructions meets the requirement, terminating, otherwise, continuing to randomly select one instruction; s3, if the instruction has no operand, skipping to S2, otherwise, continuing; s4, calculating the maximum number of instructions possibly related to the current instruction generation in the instruction context; s5, analyzing the current instruction; s6, constructing a constraint relationship between the context instructions; s7, combining the formed CNF normal forms, and solving the combined CNF normal forms by using a solver; s8, if a solving result does not exist, skipping to S2; s9, if the solving result is satisfied, analyzing the solving result; s10, storing the currently generated instruction in a cache queue; and S11, skipping toS2 to continue. According to the method, the random instruction generation model meeting the constraint condition is constructed, the random instruction sequence is automatically generated, and the purposes of high-power-consumption testing and instruction execution component correctness testing under the limit condition are achieved.

Description

technical field [0001] The invention relates to a random instruction sequence generation method based on data correlation constraints, which belongs to the technical field of computers. Background technique [0002] Randomly generated instruction sequences play an important role in the development of processors by comprehensively considering the random combination of instructions, random allocation of register resources, and avoiding data dependencies during instruction execution. Random tests that traverse registers can test the availability of processor registers; mixed instruction sequences within functional units and between functional units can verify the processor at the system level; instruction sequences without data dependencies between instructions can make The no-load rate of the pipeline is greatly reduced, especially the full pipeline instruction sequence that satisfies the conditions can continue to exert pressure on the processor instruction emission and execu...

AI Technical Summary

Problems solved by technology

But this is usually not enough, because there are multiple issues, data dependency checks and other links in the instruction execution process. When the instructions programmed at the assembly instruction level are executed on the pipeline, it may cause the pipeline to idle most of the time. The purpose of the continuous full load stress test on the pipeline

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