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Memory system and data processing system for handling errors by error analysis

A technology of data processing system and memory system, which is applied in the direction of response error generation, electrical digital data processing, static memory, etc., and can solve problems such as accuracy reduction

Pending Publication Date: 2021-07-23
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

As a result, the accuracy of predictions is significantly reduced

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  • Memory system and data processing system for handling errors by error analysis
  • Memory system and data processing system for handling errors by error analysis
  • Memory system and data processing system for handling errors by error analysis

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Embodiment Construction

[0035] Figure 1A is a diagram showing the configuration of the data processing system according to the first embodiment. Throughout the specification, references to "first embodiment", "second embodiment", "third embodiment", "embodiment" etc. do not necessarily refer to this embodiment only. Although various features of the invention are described in the context of one embodiment, the various features of the invention can be applied in multiple embodiments.

[0036] refer to Figure 1A , the data processing system according to the first embodiment may include a host 102 and a memory system 110 . The memory system 110 may include a plurality of memory devices 1501-1508. The host 102 may include an error information collection unit 1021 , a first error analysis unit 1023 , a second error analysis unit 1024 , an error handling operation unit 1025 and a host error correction code (ECC) unit 1026 .

[0037] Each of the memory devices 1501 to 1508 may include a plurality of memo...

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Abstract

The present invention relates to a data processing system comprising: a memory system comprising: a plurality of memory devices, wherein each of which comprises a first error correction unit and a plurality of cell array regions each having a plurality of memory cells coupled in an array to a plurality of word lines and a plurality of bit lines; and a host comprising a second error correction unit for correcting an error of data transferred from the memory system, and suitable for generating error correction information on the error correction operation of the second error correction unit, setting error correcting strengths to the respective memory devices using the error correction information and log information, and performing counter-error operations on the respective memory devices according to the error correcting strengths.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2020-0001998 filed on January 7, 2020, which is hereby incorporated by reference in its entirety. technical field [0003] Various embodiments relate to a data processing system, and more particularly, to a memory system capable of selecting an error response operation through error analysis and a data processing system including the memory system. Background technique [0004] Computing devices or wired / wireless electronic devices, such as computing devices such as servers, desktop computers, and laptop computers, or electronic devices such as mobile phones, game consoles, TVs, and projectors, can generate and process large amounts of data during the course of operation. In order to store data generated and processed during the course of operation, a memory system utilizing a memory device, ie a data storage device, can generally be used. A data s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10G06F11/07G06F11/34
CPCG06F11/1064G06F11/0778G06F11/1044G06F11/3476G11C29/44G11C2029/1202G11C2029/1204G11C2029/0411G11C29/26G06F11/1048G06F11/1008G06F11/0793G06F2201/88G06F11/1068G06F11/0787G06F11/079G06F11/3037
Inventor 沈应辅安南永
Owner SK HYNIX INC