Eureka AIR delivers breakthrough ideas for toughest innovation challenges, trusted by R&D personnel around the world.

A Clock Legalization Method Based on Heterogeneous FPGA Layout

A clock and layout technology, applied in the field of VLSI physical design automation, can solve problems such as design complexity and scale increase, and achieve the effect of avoiding wiring failures

Active Publication Date: 2022-07-15
FUZHOU UNIV
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Relatively, its design complexity and scale are also increasing, which brings great challenges to heterogeneous FPGA layout

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A Clock Legalization Method Based on Heterogeneous FPGA Layout
  • A Clock Legalization Method Based on Heterogeneous FPGA Layout
  • A Clock Legalization Method Based on Heterogeneous FPGA Layout

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] like figure 1 As shown, this embodiment provides a clock legalization method based on heterogeneous FPGA layout, including the following steps:

[0027] (1) Establish a mathematical model of clock constraints.

[0028] The concrete realization method of step (1) is:

[0029] First, for the FPGA clock constraint, the following representation is made: use module v i The coordinates of the center (x i , y i ) to represent its position, let C k is the index set of the block connected by clock k, namely {v i |i∈C k }. Let R be the set of clock regions, j∈R, let Represents the x-coordinate of the left and right boundaries of clock region j. Represents the y-coordinates of the upper and lower boundaries of clock region j. When the bounding box of the clock load overlaps the clock region, the clock is located in the clock re...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a clock legalization method based on heterogeneous FPGA layout. Two steps to legalize clock constraints. This method is beneficial to legalize the clock and avoid clock nets violating clock constraints during the layout process.

Description

technical field [0001] The invention belongs to the technical field of VLSI physical design automation, and in particular relates to a clock legalization method based on heterogeneous FPGA layout. Background technique [0002] Heterogeneous Field Programmable Gate Array (FPGA) is a popular FPGA chip at present, because it can realize a variety of functions, has higher performance, and can meet various needs. Relatively, its design complexity and scale are also increasing, which brings great challenges to heterogeneous FPGA layout. [0003] The optimization goal of FPGA layout is usually line length, while considering routability, timing and power consumption. In current FPGA designs, there may be hundreds of global clocks. Due to the limited clock routing resources of the current FPGA chip, we need to consider the location of the clock net in the layout stage to avoid the failure of clock net routing in the routing stage. [0004] The FPGA chip is divided into multiple cl...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/34G06F111/04G06F117/04
CPCG06F30/34G06F2111/04G06F2117/04
Inventor 陈建利杨薇林智峰
Owner FUZHOU UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com